VMOS Transistors Research Articles

The efficiency of a feedforward amplifier with delay loss

In most applications using the feedforward linearization technique, the overall amplifier efficiency is of significant concern. This paper theoretically analyzes the effect that the insertion loss of the time delay elements has on the overall efficiency of a feedforward amplifier. Practical linearity and efficiency results are given for a feedforward system, using VMOS transistor class C main and error amplifiers, to illustrate the effectiveness of the analysis.< <ETX xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">&gt;</ETX>

1/f noise in VMOS power transistors

The 1/f noise in power VMOS transistors has been measured. In the ohmic device channel the number fluctuation is comparable with that in other MOS devices but is more variable with gate voltage. In saturation, the noise and DC characteristics were measured at constant temperature using pulsed methods. Using a model of the device operation and the measured ohmic channel noise, the measured noise in saturation was compared with the calculated value. Reasonable agreement was found except for a peak just before saturation. This is ascribed to a non-uniform defect distribution along the channel.

4510439 Digital circuit multi-test system with automatic setting of test pulse levels

A pair of complementary VMOS transistors connected in push-pull is utilized to convert pulses supplied to the gates of these transistors into two-level output signals of which each of the voltage levels is independently adjustable. A digital-to-analog converter is connected to each of the VMOS transistor channels inputs, so that the two voltage levels in question can be set and changed by digital input to the converters provided by a microprocessor. Controlling the d.c. levels of output pulses by a microprocessor makes possible the testing of electronic circuits utilizing different kinds of electronic logic with a single test unit. The selection of the voltage levels of the output pulses to match the type of logic of the circuits to which the pulses are applied can be made through the microprocessor in response to a signal representative of the supply voltage of the circuits under test.

Experimental verification of a VMOS UHF power transistor model and design

A high-frequency model for VMOS power transistors has been developed. Using this model a VMOS transistor was designed to achieve 10 dB maximum stable gain at a frequency of 1 GHz. In the design the static parameters of breakdown voltage and on-resistance were also optimised. The experimental results verified the model and showed excellent agreement.

MOS power transistor and ceramic thyratron for fast high voltage pulser

A high reliability circuit has been developed in order to trigger a ceramic thyratron. The necessity of building a system highly protected from voltage and current glitches is due to the particular loads with are to be driven by the thyratron. In the circuit design, VMOS (both with ‘p’ or ‘n’ channel) and HEXFET transistors have been used. A delay time of about 60 ns between the NIM input signal and the thyratron grid voltage peak has been obtained. The delay between the NIM input signal and the thyratron trigger is about 80 ns. This apparatus has been developed in order to drive a high voltage generator, used with a self-shunted streamer chamber.

An effect of semiconductor surface shape on gate breakdown voltage of a VMOS transistor

An effect of semiconductor surface shape on gate breakdown voltage of a VMOS transistor

Numerical comparison of DMOS, VMOS, and UMOS power transistors

Two-dimensional simulation of breakdown voltage and on-resistance of DMOS, VMOS, and UMOS vertical power devices is performed. The three devices are evaluated for breakdown-voltage designs of 100, 550, and 1000 V.

Distributed model for DMOS and VMOS transistors

The paper presents a new model valid for MOS transistor static analysis. The model takes into account the impurity concentration variation along the channel. The calculations done upon several DMOS and VMOS transistors were in good accordance with the experimental determinations and with the results pointed out by other more complex models.

A Compact Modular High Voltage System for Phototube and MWPC Applications

This high voltage system consists of a 64 channel CAMAC control module and various power modules which can optionally be located in CAMAC crates. Power is generated by VMOS transistors in a high frequency, high efficiency circuit. A table driven processor in the control module provides a variety of self-monitoring features without the software complexity of a microprocessor.

Apparatus with nanosecond field transition times for field reversal studies of surface processes at high temperatures

A new type of field-reversal apparatus is described. It is intended for desorption and surface reaction studies in systems with surface ionization. The problems of mechanically modulating the molecular beam are circumvented by instead reversing the electric field outside the surface and thus perturbing the steady-state desorption conditions. The short field reversal time of ⩽ 10 ns with a 90 V voltage step is reached by using VMOS transistors with optoisolated driving circuits. The ions from the ionizing surface are converted to electrons on a Cu–Be dynode. The electrons give photons in a scintillator, and the photons are detected by a photomultiplier outside the vacuum wall. The apparatus dependent signal rise time is around 40 ns, which means that surface processes with very short characteristic time constants can be measurable.

A theoretical and experimental analysis of the buried-source VMOS dynamic RAM cell

The buried-source dynamic RAM cell combines a VMOS transistor (VMOST) and a buried junction capacitor to make a one-transistor cell (1TC) providing large storage capacitance, long charge retention, and high density. The threshold voltage, breakdown voltage, and weak inversion current for the forward and reverse modes of operation of the VMOST and the junction capacitance are experimentally related to the nonuniform doping profile of the channel. Equations are developed for the VMOST short-channel threshold voltage and storage capacity of the cell. The charge capacity (per unit of cell area) of the buried-source cell is calculated to be 2.5 times that of the conventional 1TC cell. The cell charge retention time was measured at more than 1 s at 100°C, proving operation of the device as a dynamic memory element. The technology is capable of producing an 80-µm <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sup> cell using 4-µm minimum features, no cell contacts, and a single level of interconnect.

Optimization of nonplanar power MOS transistors

Analysis of fundamental MOSFET parameters predicts device limits in high-voltage high-speed operation that exceed the performance of bipolar devices. The optimization of voltage, speed, and on resistance parameters for power MOSFET's suggests a vertical three-terminal device design with short, wide channels; a wide, lightly doped drain region; and field terminator rings at the device perimeter. Utilizing this design philosophy, VMOS transistors have been produced with source-drain breakdown voltage greater than 450 V, and 5.5-Ω on resistance for 2.0-mm2active area. With a high channel width packing density design and 2.5-mm2active area, a 30-V transistor has also been produced having only 0.060-Ω on resistance. The breakdown voltage and on resistance of these devices exceed the performance of other power MOSFET's currently available. Also, the switching speed of these devices (better than 15 ns) far exceeds the performance of high-voltage bipolar transistors. Measurements of drain leakage current at 200-V drain potential show a resistance ratio R_{off}/R_{on} of approximately 1010for a 20-V variation in gate-to-source voltage.

VMOS technology applied to dynamic RAMs

A seven-mask VMOS process has been developed for dynamic RAMs with self-aligned VMOS and planar Al-gate transistors. Using 4 /spl mu/m photolithography, one-transistor cells with a cell size of 150 /spl mu/m/SUP 2/ have been realized. The read signal at the bit line is more than 200 mV. Implementations of a sense amplifier and a word-line driver show that those circuits determine the smallest word and bit line spacing. The paper is concluded by a proposal for a 64K RAM with a chip size of 21 mm/SUP 2/ using 4 /spl mu/m design rules.

A complementary DMOS-VMOS IC structure

A new complementary MOS structure has been fabricated consisting of a p-channel DMOS transistor and an n-channel double-diffused VMOS transistor. The transconductance of each transistor was between 0.85-0.98 of the theoretical g m . The threshold voltages have been adjusted by either ion implantation or by adjusting the diffusion profiles. The inverter operation is similar to that of standard CMOS.

A VMOS-bipolar compatible technology for high-performance analog integrated circuits

A new integrated circuit process is presented which permits the simultaneous fabrication of n-p-n bipolar transitors and p-channel silicon-gate VMOS transistors. The technology involves no extra processing steps compared to the bipolar process. Test results are presented for the resulting VMOS devices.

VMOS—A new MOS integrated circuit technology

A new V-groove MOS integrated circuit technology (VMOS) is described. It makes use of preferential etching of silicon to define the channels of the MOS transistors. The fabrication involves either a three or four mask process and is capable of producing either silicon gate or standard metal gate transistors. The technology results in very short channel length devices using non-critical alignment tolerances. Despite the short channel length, the VMOS transistor exhibits lower output conductance and higher breakdown voltage than a standard MOS transistor. A first order theory is presented for the VMOS transistor along with measurements made on test devices of various channel lengths. Some integrated circuit applications of the technology are also presented, including an R- S fiip-flop and a 27-stage bucket brigade shift register. The advantages of the VMOS technology in such applications are discussed.