VME Modules Research Articles

Implementation of the DAQ software in the ALTI Module of the ATLAS TileCal

The Tile Calorimeter (TileCal) is the central hadronic calorimeter (|η| < 1.7) of the ATLAS experiment, made out of iron plates and plastic scintillators. The TileCal is divided into three barrels along the beam axis, each of which is azimuthally segmented into 64 wedge-shaped modules, staggered in the 0 direction. TileCal online software is a set of Trigger and Data Acquisition (TDAQ) software, and its main purpose is to readout, transport and store physics data originating from collisions at the Large Hadron Collider (LHC). The ATLAS Local Trigger Interface (ALTI) module is a new electronic board, designed for the ATLAS experiment at CERN, a part of the Timing, Trigger and Control (TTC) system. It is a 6U VME module which integrates the functionalities of four legacy modules, currently used in the experiment: Local Trigger Processor, Local Trigger Processor interface, TTC VME bus interface and the TTC emitter. ALTI module will provide the interface between the Level-1 Central Trigger Processor and the TTC optical broadcasting network to the Front-End (FE) electronics of each of the ATLAS sub-detectors. There is a need to develop and integrate the ALTI software in the Tile online software. Performance tests and maintenance of the ALTI module software will be carried out during the Long Shutdown 2 period (LS2), in preparation for Run 3 data-taking period.

Development of Next-Generation LLRF Control System for J-PARC Rapid Cycling Synchrotron

The low level rf (LLRF) control system for the rapid cycling synchrotron (RCS) of the Japan Proton Accelerator Research Complex (J-PARC) started its operation in 2007. The key functions of the LLRF control system are the dual harmonic auto voltage control, which generates superposed voltages of the fundamental accelerating harmonic and the second harmonic in a single wideband magnetic alloy (MA) cavity, and the multiharmonic rf feedforward to compensate the beam loading in the MA cavity caused by high intensity beams. These functions are necessary to accelerate high intensity proton beams. The system has been working well without major problems for more than ten years. However, the old FPGAs (Xilinx Virtex-II pro etc.) are discontinued and not supported by the current development environment. It will be difficult to maintain the system in near future. Thus, we are planning to replace the existing VME-based LLRF control system with a new MicroTCA.4 based system. The system controls twelve cavities independently and calculates vector sum of the cavity voltages in real time for phase feedback. Signal and data transfer between the modules is a key to realize the functions. In the existing system, the transfer is implemented not only the backplane but also serial link via cables between the VME modules. It is much more simplified in the new system thanks to the high speed communication capability of the MicroTCA.4 backplane. In this article, we describe the configuration of the system under development, the implemented functions, and preliminary test results.

A tailored 200 parameter VME based data acquisition system for IBA at the Lund Ion Beam Analysis Facility – Hardware and software

With the recent advances towards modern Ion Beam Analysis (IBA), going from one- or few-parameter detector systems to multi-parameter systems, it has been necessary to expand and replace the more than twenty years old CAMAC based system. A new VME multi-parameter (presently up to 200 channels) data acquisition and control system has been developed and implemented at the Lund Ion Beam Analysis Facility (LIBAF).The system is based on the VX-511 Single Board Computer (SBC), acting as master with arbiter functionality and consists of standard VME modules like Analog to Digital Converters (ADC’s), Charge to Digital Converters (QDC’s), Time to Digital Converters (TDC’s), scaler’s, IO-cards, high voltage and waveform units. The modules have been specially selected to support all of the present detector systems in the laboratory, with the option of future expansion. Typically, the detector systems consist of silicon strip detectors, silicon drift detectors and scintillator detectors, for detection of charged particles, X-rays and γ-rays.The data flow of the raw data buffers out from the VME bus to the final storage place on a 16 terabyte network attached storage disc (NAS-disc) is described. The acquisition process, remotely controlled over one of the SBCs ethernet channels, is also discussed. The user interface is written in the Kmax software package, and is used to control the acquisition process as well as for advanced online and offline data analysis through a user-friendly graphical user interface (GUI). In this work the system implementation, layout and performance are presented. The user interface and possibilities for advanced offline analysis are also discussed and illustrated.

Preliminary results on time-resolved ion beam induced luminescence applied to the provenance study of lapis lazuli

This work will present preliminary results concerning the use of time-resolved ion beam induced luminescence applied to provenance studies of lapis lazuli. Measurements were performed at the pulsed beam facility at LABEC laboratory in Florence. Lapis lazuli is a semi-precious gemstone, used as ornament since the early civilizations that can be found in few places on Earth. The importance of this work lies in understanding the origin of various samples of lapis lazuli, from which it may be possible to gain insight into trade routes from ancient times. The samples studied in this work originated from Chile, Afghanistan, Tajikistan, Myanmar, and Siberia. The stones were irradiated with 3MeV protons and the resulting luminescence was detected by a photomultiplier tube, whose output was acquired using a sampling digitizer VME module (CAEN/V1720). Wavelength discrimination was performed at 430nm utilizing a range of beam currents. The results showed that, by changing the beam current intensity, one can study different features of lapis lazuli, and this may aid in distinguishing lapis lazuli from different provenances.

A High-Density Time-to-Digital Converter Prototype Module for BES III End-Cap TOF Upgrade

This paper describes a high-precision time measurement module for the end-cap time-of-flight (ETOF) upgrade of the Beijing Spectrometer (BES III). ETOF is scheduled to be upgraded with the multi-gap resistive plate chambers (MRPCs) instead of a scintillator. The new ETOF of BES III will have 1728 readout channels, which is a big challenge for the readout electronics. The time resolution of the readout electronics system is required to be better than 25 ps. A 9U VME module with 72 time measurement channels is designed to perform the time measurement. The signals, which are produced by the detector and then amplified and discriminated by the attached frontend electronics, are sent to this module. The module, which is named TDIG, uses the CERN HPTDC to achieve high-precision time measurement. There are nine HPTDC chips on the module, and each provides eight channels to realize 72 channels. A series of experiment tests show that the time resolution of the TDIG module is better than 20 ps. We have constructed a beam test system composed of six plastic scintillators, two MRPC modules, and ETOF prototype electronics, which testifies to the time resolution expected. An overall time resolution of less than 45 ps for beam events has been achieved.

Data acquisition and online monitoring software for CBM test beams

The Compressed Baryonic Matter (CBM) experiment is intended to run at the FAIR facility that is currently being built at GSI in Darmstadt, Germany. For testing of future CBM detector and read-out electronics prototypes, several test beam campaigns have been performed at different locations, such as GSI, COSY, and CERN PS. The DAQ software has to treat various data inputs: standard VME modules on the MBS system, and different kinds of FPGA boards, read via USB, Ethernet, or optical links. The Data Acquisition Backbone Core framework (DABC) is able to combine such different data sources with event-builder processes running on regular Linux PCs. DABC can also retrieve the instrumental set-up data from EPICS slow control systems and insert it into the event data stream for later analysis. Vice versa, the DIM based DABC control protocol has been integrated to the general CBM EPICS IOC by means of an EPICS-DIM interface. Hence the DAQ can be monitored and steered with a CSS based operator GUI. The CBM online monitoring analysis is based on the GSI Go4 framework which can directly connect to DABC online data via sockets, or process stored data from list-mode files. A Go4 sub-framework has been implemented to provide possibility of parallel development of analysis code for different sub-detectors groups. This allows divide the Go4 components up into independent software packages that can run either standalone, or together at the beam-time in a full set-up.

LLRF and timing system for the SCSS test accelerator at SPring-8

The 250MeV SCSS test accelerator as an extreme-ultra violet (EUV) laser source has been built at SPring-8. The accelerator comprises a 500kV thermionic gun, a velocity bunching system using multi-sub-harmonic bunchers (SHB) in an injector and a magnetic bunch compressor using a chicane of 4 bending magnets, a 5712MHz main accelerator to accelerate an electron beam up to 250MeV, and undulators to radiate the EUV laser. These bunch compression processes make short bunched electrons with a 300A peak current and a 300fs pulse width. The pulse width and peak current of an electron beam, which strongly affect the pulse width and intensity of the laser light, are mainly decided by the pulse compression ratio of the velocity bunching and the magnetic bunch compressing processes. The compression ratio is also determined due to an energy chirp along the beam bunch generated by an off-crest rf field at the SHB and cavities before the chicane. To constantly keep the beam pulse-width conducted by rf and timing signals, which are temporally controlled within subpicoseconds of the designed value, the low-level rf and timing system of the test accelerator has been developed. The system comprises a very low-noise and temporally stable reference signal source, in-phase and quadrature (IQ) modulators and demodulators, as well as VME type 12 bits analog-to-digital and digital-to-analog converter modules to manipulate an rf phase and amplitude by IQ functions for the cavity. We achieved that the SSB noise of the 5712MHz reference signal source was less than −120dBc/Hz at 1kHz offset from the reference frequency; the phase setting and detecting resolution of the IQ-modulators and demodulators were within +/−0.5° at 5712MHz. A master trigger VME module and a trigger delay VME module were also developed to activate the components of the test accelerator. The time jitter of the delay module was less than 0.7ps, sufficient for our present requirement. As a result, a beam energy variation of 0.06% was achieved and a time jitter of 46fs between the acceleration rf signal and the beam was realized.

The central trigger control system of the CMS experiment at CERN

The Large Hadron Collider will deliver up to 32 million physics collisions per second. Thisrate is far too high to be processed by present-day computer farms, let alone stored on disk by the experiments for offline analysis.A fast selection of interesting events must therefore be made. In the CMS experiment,this is implemented in two stages: the Level-1 Trigger of the CMS experiment uses custom-made, fast electronics,while the experiment's high-level trigger is implemented in computer farms. The Level-1 Global Triggerelectronics has to receive signals from the subdetector systems that enter the trigger (mostly from muon detectorsand calorimeters), synchronize them, determine if a pre-set trigger condition is fulfilled, check if thevarious subsystems are ready to accept triggers based on information from the TriggerThrottling System and on calculations of possible dead-times, and finally distribute the trigger decision(``Level-1 Accept'') together with timing signals to the subdetectors over the so-called ``Trigger, Timing and Control'' distribution tree of the experiment. These functions are fulfilled by severalspecialized, custom-made VME modules, most of which are housed in one crate. The overallcontrol is exerted by the central ``Trigger Control System'', which is described in this paper.It consists of one main module and several ancillary boards for input and output functions.

Multi-channel picosecond photon timing with microchannel plate detectors

Microchannel plate-based detectors have the capability to photon-count at time resolutions which outperform solid-state devices such as the APD or SiPM, and have a geometry that lends itself to pixelated readouts. We describe a multi-channel, photon-counting microchannel plate detector optimised for photon timing in the picosecond regime. The detector was originally developed for application to time-resolved spectroscopy in the life sciences, however its performance characteristics make it suitable for applications where high time resolution and multi-channel photon-counting are required including Cherenkov light detection in nuclear physics, particle physics, and astroparticle astronomy. We describe the prototype detector, a sealed tube device comprising an optical photocathode proximity focussed to a small pore microchannel plate stack. Event charge is collected on a multi-channel readout comprising an 8×8 pixel array, manufactured on a multilayer ceramic, which provides vacuum integrity for the detector enclosure and a multi-way electrical feedthrough for the readout array. Each pixel addresses one channel of a NINO ASIC, a multi-channel preamplifier–discriminator device. The discriminator outputs are timed to 25 ps by the HPTDC time-to-digital converter ASIC, which uses a time-over-threshold technique for amplitude walk correction. We present performance measurements using a pulsed laser of the 64 channel prototype system comprising a 25 mm detector, NINO front-end, and a CAEN V1290A VME module utilising HPTDC. We discuss the next phase in the project—design and manufacture of a 40 mm detector with a 16×16 pixel 2 readout coupled to custom NINO/HPTDC electronics constructed as a series of 64 channel modules, expandable to even larger channel densities.

Electronics of BESIII TOF Monitor System

This paper describes the control electronics for the time of flight (TOF) monitor system of BESIII. A 9U VME module is designed as the interface between the TOF monitor laser box and BESIII data acquisition system. It takes charge of enabling the laser source, sending trigger signals to the laser driver, controlling the optic path, and measuring the charge and arrival time of pulses from two reference phototubes. The module also sends a Level 1 trigger to the TOF readout system, after each trigger pulse to the laser source. The interface and control logic are implemented in one Altera field-programmable gate array, and signals from the reference PMTs of the laser system are digitized with the CERN HPTDC technique. A series of experimental tests show that the time resolution of the monitor electronics is better than 25 ps, and the relative methodical error of the charge measurement is less than 0.5% after quadratic fitting. The TOF monitor system was installed at the end of 2007 and has been operating continuously since then. A total time resolution of about 70 ps and a charge resolution of about 4% of the TOF counters have been obtained during field monitor tests.

Online data processing and hit time reconstruction for silicon detector readout

A major upgrade of the KEKB factory (Tsukuba, Japan) is foreseen until 2013, aiming at a luminosity of up to 8 × 10 35 cm - 2 s - 1 , which is about 40 times the present value. Accordingly, a similar increase is expected for trigger rate and occupancy of the Silicon Vertex Detector (SVD). The current readout system has a shaping time of 800 ns, no multi-event memory and thus requires a trigger within this period. As it already operates at its limit, it obviously has to be replaced for the upgrade. We developed a readout system using the APV25 chip with a shaping time of 50 ns and an integrated analog pipeline. By taking six consecutive samples of the shaper output and processing these data with FPGAs on a VME module we can determine timing information of the hits with a precision of about 3 ns RMS, which enables occupancy reduction and thus eases subsequent track finding. Thanks to reading several samples the system can tolerate a trigger jitter of up to ± 2 clocks. A dedicated pipelined data processor is implemented for each input, which encodes position, pulse height and time information of a hit in a single 32 bit word. The acceptable trigger rate is limited by the time needed to read out six samples from the APV25.

A novel VME based SR data acquisition system at PSI

A new data acquisition system (DAQ) for bulk μ SR and low-energy μ SR (LE- μ SR) has been developed at PSI. It is based on commercial and in-house VME modules, and on the MIDAS DAQ software library. The system is able to cope with the different needs of the various PSI μ SR spectrometers, which was not possible with the existing CAMAC and ORTEC's pTA-clock based DAQ systems. The VME clock is a 64-channel CAEN V1190 TDC, using the CERN HPTDC chip, with programmable time resolution of 25, 100, 200 or 800 ps. The TDC onboard memory is continuously read through the VME bus by standard PC's or dedicated servers, using a 1-Gbit/s SIS3100/1100 VME–PCI interface. Detector rates are independently monitored using a 32-channel SIS3820 scaler module. In-house developed modules comprise an 8-channel constant fraction discriminator CFD950, a CD950 clock divider, an 8-channel linear fan-out SP950, a 16-channel NIM-ECL level converter LC950, and a programmable coincidence module FC950. All modules feature a superior performance compared to commercially available devices which allows their use also in the planned high-field μ SR spectrometer where a time resolution of about 100 ps is envisaged. A special external hardware logic is no longer required, since the system can deal with a rate total of 5 MHz which is sufficient for μ SR spectrometers with high event rate in their active veto systems.

Readout of silicon strip detectors with position and timing information

Low-noise front-end amplifiers for silicon strip detectors are already available for decades, providing excellent signal-to-noise ratio and thus very precise spatial resolution, but at the cost of a long shaping time in the microsecond range. Due to occupancy and pile-up issues, modern experiments need much faster electronics. With submicron ASICs, adequate readout and data processing, it is possible to obtain not only spatial hit data, but also accurate timing information—a feature which is rarely exploited so far. We present the concept of a silicon vertex detector readout system intended for an upgrade of the Belle experiment at KEK (Tsukuba, Japan). The APV25 front-end chip, originally developed for CMS at CERN, is used in a way where it delivers multiple samples along the shaped waveform, such that not only the analog pulse height, but also the timing of each particle hit can be determined. We developed a complete readout system including an FADC + Processor VME module which performs zero-suppression in FPGAs. The hit time measurement is also planned on the same module. As fast amplifiers are inherently more susceptible to noise, which largely depends on the load capacitance, the front-end chips should be located as close to the detector as possible. On the other hand, the material budget, especially in a low-energy electron–positron machine such as Belle, should be minimized. We tried to merge those demands with a fully functional “Flex_Module”, where thinned APV25 readout chips are mounted on the silicon sensor.

Upgrade of the Level 1 Global Trigger System in the Belle Experiment

In this paper, we describe design and development of the new global decision logic units for the Belle detector at the KEK B-factory. The new units consist of two identical 9U VME modules which are designed using the programmable logic techniques. Each module has an inexpensive programmable logic device that has high density input and output lines. Performance tests of these new modules and existing system are compared and showed good results. Utilizing the nature of the logic device on the board, we also examine possibility of the implementation of an artificial neural network algorithm to the new trigger board for a more efficient data acquisition.

Performance and response of scintillating fiber modules to protons and pions

The HERMES experiment located at DESY measures scattering reactions of 27.5GeV positrons or electrons impinging on a gaseous hydrogen target. The target will be surrounded by a recoil detector dedicated to measure recoiling nucleons. This detector will operate a scintillating fiber tracker to identify and track protons for momenta up to 1400MeV/c. Scintillating fibers are an ideal tool to combine energy and position measurements for charged particles in an intermediate momentum range. They offer a high granularity while keeping the mechanical construction and material density at a minimum. Modules build from Kuraray SCSF-78 fibers of 1mm diameter were tested at a secondary beam of positive charge at various momenta from 300 to 900MeV/c. Their read-out was performed using customized VME modules with front-end boards based on GASSIPLEX chips. The energy response and particle identification properties of the modules were tested. The results obtained in this study meet the specified design criteria.

Verification of the GREAT Total Data Readout System Using Pseudo Random Pattern Generator

Total Data Readout (TDR) is a powerful data acquisition tool developed for use with Recoil Decay Tagging (RDT) experiments on the GREAT (Gamma, Recoil, Electron, Alpha Tagging) spectrometer. RDT experiments correlate prompt radioactive decays detected at the target position with subsequent decays of recoiling reaction products implanted in GREAT, located at the focal plane of the RITU recoil separator, several microseconds later. TDR uses independent channels associated in a software event builder based on timestamps to form a single time ordered data stream. It is crucial to maintain the accuracy of the timestamps over long periods (microseconds to hours) for the study of Exotic Nuclei. The TDR system cannot be tested fully by use of calibrated sources with GREAT and a novel method of verifying the system is required. Our solution is to use the predictable randomness of a Pseudo Random Number generator based on Linear Feedback Shift Registers (LFSR) implemented in a 16 channel VME module. The random value defines the delay between pulses into the TDR system. The recorded results are sorted and checked for correspondence with the LFSR sequence. We show the method, design of the module, and discuss the results and benefits of the tests

Progress of data processing system in JT-60—Development of remote experiment system

JT-60 data processing system (DPS) possesses three-level hierarchy. At the top level of hierarchy is JT-60 inter-shot processor (MSP-ISP), which is a mainframe computer, provides communication with the JT-60 supervisory control system and supervises the internal communication inside the DPS. The middle level of hierarchy has minicomputers and the bottom level of hierarchy has individual diagnostic subsystems, which consist of the CAMAC and VME modules. To meet the demand for advanced diagnostics, the DPS has been progressed in stages from a three-level hierarchy system, which was dependent on the processing power of the MSP-ISP, to a two-level hierarchy system, which is decentralized data processing system (New-DPS) by utilizing the UNIX-based workstations and network technology. At present, replacing the MSP-ISP with a UNIX-based workstation is under way as a final phase in building the New-DPS project. This replacement will be accomplished by October 2005. In addition, remote experiment in JT-60 is considered to be an important issue in extension of the collaborative research among the nuclear fusion community. Technical environments for this task have been developed. The participant from a remote site can set discharge parameters with assistance of the dedicated machine operating status-information tools.

A 48 channel pulse shape digitizer with DSP

A 48 channel, 40-65 MS/sec., 10 bit pulse shape digitizer card has been designed in the VME-6U form factor. The design uses 6 octal Flash Analog to Digital Converter (FADC) chips (ADS5121 or ADS5122) from Texas Instruments. The FADCs are read out by 6 Altera Cyclone FPGAs. A 7th FPGA is used to collect and merge the event fragments. The present firmware includes trigger latency buffers, waveform segment buffers, real-time digital filtering, time stamp generation, amplitude evaluation, event formatting and buffering, plus a simple VME A24D32 interface. The design also includes a source synchronous bi-directional serial LVDS link for the interconnection of the modules to a large system. The first version of the module is designed for an R&D test readout system connected to a few hundred drift chamber cathode pads or TPC cathode/anode pads. The final version is intended for the readout of the KOPIO preradiator cathode drift chamber pads (/spl sim/75000 channels). This version will only have the LVDS interconnect. The present design using off-the- shelf commercial components is an interesting alternative to an ASIC approach for intermediate size readout system. It occupies about 3 times the area of an equivalent ASIC system, and has comparable power dissipation. In its present form, the development version of the module can be useful as a general purpose waveform digitizer and DSP with its high density (48 channels per single width VME module) at a relatively low cost per channel.

The host software for the real-time PHA X-ray diagnostic on TCV

A real-time pulse height analysis (PHA) X-ray diagnostic for the TCV tokamak has been developed using CFN multi-DSP-based VME acquisition, processing and control board. The hardware is composed by: (i) a detection system based on a Si SDD detector; (ii) a VME host running Linux; (iii) a on-site developed VME module having 4 acquisition, processing and control (APC) channels. The software system was designed in order to allow a native integration with MDSplus. A complete software development cycle is presented. A support library to the VME module has been developed. A shareable application level library was also developed. A set of MDSplus Tree Data Interface (TDI) scripts was developed on top of the application shareable library. The scripts are used to build a software daemon. The daemon programmes the module with the chosen diagnostic parameters. It also performs data collecting and board monitoring functions. Data is stored in an MDSplus tree.

Control and data acquisition system for the multiple cell array detector of the TJ-II heavy ion beam diagnostic

A dedicated control and data acquisition system for the multiple cell array detector (MCAD) of the TJ-II heavy ion beam diagnostic (HIBD) has been developed, based on in-house designed VME modules and Linux. The software and hardware architecture and its implementation are described in this paper. The hardware consists of: (i) a VME host running Linux; (ii) four CFN transient recorder boards; (iii) an analogue output board; (iv) a commercial 32 bit TTL I/O M-Module mezzanine. The software for the active control of the primary and secondary beam lines has two major components: (i) a server daemon running on the VME host, receiving operation parameters and waveforms to be programmed and controlling board operation; (ii) client applications with graphical user interfaces running on the control room PC's. The software for the MCAD acquisition system consists of a daemon controlling acquisition and writing data to the TJ-II database, and a graphical application allowing easy configuration of acquisition parameters.