The complexity involved in VLSI creates the need to automate chip design as far as possible and to perform design decisions on a very high level. To support this task high-level CAD systems are needed. To ensure that the layouts produced by those systems meet a given specification, optimizations have to be performed. One of the problems to be solved in high-level optimization is that of performing operations without a clear knowledge of the real objective function. The absence of adequate information causes hard problems to become even harder to solve. Therefore we present some ideas to support VLSI chip design. This is done by providing predictions about the consequences of design decisions in early stages. In this paper we consider the problem of predicting the silicon area consumption of a module after placement and routing. These estimates are calculated by algorithms which perform a partial synthesis. Furthermore, formulas are deduced using characteristics of VLSI modules to estimate the routing area expenditures relative to a design system.
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