VLSI Layout Verification Research Articles

Subcircuit Pattern Recognition in Transistor Level Circuits

The paper presents a computer program for automatically extracting the hierarchy of a large-scale digital circuit from its transistor-level description derived from the layout of VLSI circuit. The considered problem arises in VLSI layout verification as well as in the circuit reengineering. The proposed subcircuit recognition algorithm extracts functional level structure from transistor-level circuit collecting transistors into gates without using any predefined cell library. The algorithm comes from a SPICE like network description and realizes three-step process. First, a structural approach in which gate structures are recognized as channel connected sequences of transistors is used. Then channel connected sequences of transistors which implement CMOS gates are searched for. And finally the method of subcircuit pattern recognition is used to gather the rest sequences of transistors into minimal number of classes of identical functional blocks. The presented algorithm has been implemented as a program in C++ and tested using practical transistor-level circuits.

Parallel Algorithms for VLSI Layout Verification

Layout verification determines whether the polygons that represent different mask layers in the chip conform to the technology specifications. Commercial layout verification programs can take tens of hours to run in the flattened representations for large designs. It is therefore desirable to run the DRC problem in parallel to reduce the runtimes. Also, the memory requirements of large chips are such that the entire chip description may not fit in the memory of a single workstation; hence, parallel processing allows one to distribute the memory requirements of the problem across multiple processors. In this paper, we will present a parallel implementation of a design-rule-checking program called ProperDRC which is implemented on top of the ProperCAD environment. ProperDRC has two novel contributions over previous work. First, it is portable across a large number of multiprocessor platforms, including shared memory multiprocessors, message-passing distributed memory multiprocessors, and hybrid architectures comprised of uni- and multiprocessor workstations connected by a network. Second, ProperDRC is able to exploit multiple levels of parallelism. It can utilize data parallelism, task parallelism, or a simultaneous combination of the two types of parallelism to perform DRC operations concurrently on a multiprocessor architecture. This paper presents specifics of the implementation of ProperDRC, provides an analysis of the methods used to obtain parallelism, addresses load balancing issues, and reports on experimental results on various benchmark circuits.

Boundary element methods for 3D capacitance and substrate resistance calculations in inhomogeneous media in a VLSI layout verification package

In this paper the application of the boundary element method to the layout verification of VLSI designs is described. The methods for the calculation of interconnection capacitances and substrate resistances with the use of problem specific Green's functions are also described. The derivation of these functions for multilayer structures is presented. Emphasis is on computational efficiency and practical accuracy. These are achieved by the type of the Green's functions and an appropriate model reduction technique. The methods are implemented in the layout extractor Space.

A PC knowledge-based environment for VLSI layout verification

This article presents an integrated rule-based environment for VLSI layout verification. This environment comprises a user interface, a rule base, an inference mechanism consisting of a hierarchical design-rule checker (DRC) and a circuit extractor (EXT), and a general purpose graphics system. This environment is called CULANS Cairo University Layout ANalysi S. The inference mechanism, denoted by DRC-EXT, uses a pattern recognition approach to perform design-rule checking and circuit extraction simultaneously. It interprets the rules of the knowledge base and the data of the input layout in terms of rectangular interaction patters. Consequently, it searches the layout to discover design-rule violations or to recognize the circuit elements. To avoid the combinatorial explosion, a heuristic search is used so that the search space is considerably reduced. The implemented heuristic search exploits a branch and bound technique that has been augmented in a dynamic programming scheme. To accomplish efficient design-rule checking and circuit extraction, CULANS utilizes the internal hierarchy of the VLSI circuit to an arbitrary number of hierarchical levels.

A logic-to-logic comparator for VLSI layout verification

The logic-to-logic comparator (LLC) is described as a tool that verifies VLSI layouts by comparing the logic diagrams for a circuit with structures extracted from the circuit's layout. LLC can operate at either the gate or the transistor level, although the gate level is preferred. It is similar to other graph-isomorphism-based tools, but incorporates some important improvements. The most important of these is a path-comparison algorithm that uses dynamically calculated global information. In addition, LLC contains a gate-matching algorithm that can use certain types of symmetry to distinguish between gates that appear to be identical to less sophisticated algorithms. LLC has been used to verify several commercially available VLSI chips. >

A Hybrid Element Method For CapacitanceExtraction In VLSI Layout Verification System

In this paper we describe a hybrid element method which combines the boundary element method (BEM) and the finite element method (FEM) to calculate circuit models for layout dependent capacitances. The method can handle irregularities in the stratification of the layout of the integrated circuits (IC's). We present a stand-alone extraction program which we developed for validation and testing purposes. We show that the hybrid method can be included in our VLSI layout verification package Space.