VLSI Design System Research Articles

16-Bit Carry Look-Ahead Adder: Design and Layout with Cadence Tools Top of Form

Abstract: The development of highly organised architecture is the primary goal of the current communication world in order to achieve high speed computation with low power consumption. The Carry Look Ahead Adder is highly efficient due to its ability to reduce the propagation time of carry bits, resulting in time savings. The implementation of a 16-Bit Carry Look Ahead Adder using the Cadence tool is carried out in our project. Logical equations for carry generation (G) and carry propagation (P) are used to create the carry and sum for the 1-bit adder. Then, using the Virtuoso schematic editor, a single bit carry is developed. After that, a fresh cell view for the carry block is made and supplied as an input for adder implementations. Next, the bit rate is increased to 4 bits. Using this 4 bit adder, 8/16 bit adder is implemented using Cadence tool. It is necessary to have a basic understanding of IC design guidelines and fabrication procedures in order to produce the layout. Within the electronic VLSI design system, the layout will go through a Design Rule Check to find any breaches

June 2022: Top 10 Read Articles in VLSI design & Communication Systems

June 2022: Top 10 Read Articles in VLSI design & Communication Systems

May 2022: Top Read Articles in VLSI design & Communication Systems

May 2022: Top Read Articles in VLSI design & Communication Systems

April 2022: Top Read Articles in VLSI design & Communication Systems

April 2022: Top Read Articles in VLSI design & Communication Systems

Magnitude Comparator Realization using Threshold Logic

Threshold logic design can be regarded as an alternative method of traditional logic gate design. Threshold logic can be considered as the primary logic of brain. Neurons can be considered as threshold logic gates. Each neuron fires when its activation threshold is crossed. The basic idea behind threshold logic is threshold decision principle. Threshold decision principle checks whether the weighted sum of inputs crosses a threshold and accordingly output is defined. Several implementations for threshold logic were proposed. Resistive threshold logic is a new method for threshold logic implementation. In this paper, using the concept of resistive threshold logic, a magnitude comparator is realized. LTSpiceIV and Electric VLSI Design System are the simulation tools used in this work.

Design and Analysis of High Speed Low Power Hybrid Adder Using Transmission Gates

Addition is the vital arithmetic operation and it acts as a base for many arithmetic operations such as multipliers, dividers, etc. A full adder acts as a basic component in complex circuits. Full adder is the essential segment in many applications such as DSP, Microcontroller, Microprocessor, etc. There exists an inevitable swap between speed and power indulgence in VLSI design systems. A new modified hybrid 1-bit full adder using TG is presented. Here, the circuit is replaced with a simple XNOR gate, which increases the speed. Due to this, transistor count gets reduced results in better optimization of area. The analysis has been carried out also for 2, 4, 8 and 16 bit and it is compared with the various techniques. The result shows a significant improvement in speed, area, power dissipation and transistor counts.

Modified decimal matrix codes for error detection in memory using pipeline architecture.

31Jul 2016 Modified decimal matrix codes for error detection in memory using pipeline architecture. Anagha. K.N and Raghu.M.C. Student, VLSI design system, NCERC, Kerala, India. Assistant Professor, Department of Electronics, NCERC, Kerala, India.

Extracting Behavioral Data from Physical Descriptions of MEMS for Simulation

The work described here deals with the problems of modeling and simulation for MEMS devices. The eventual goal is to produce a top-down MEMS design system similar to today‘s powerful VLSI design systems. In this work a fixed fabrication process (MUMPS) and a fixed layout tool (L-Edit) are chosen. Thus our efforts are concentrated on reliable simulation of designs and eventual comparison with actual fabricated parts. The cantilever beam is chosen as an example of how extraction from a physical layout may be modeled and interfaced with various simulators.

Arithmetic Boolean Expression Manipulator Using BDDs

Recently, there has been a lot of works on LSI design systems using Binary Decision Diagrams (BDDs), which are efficient representations of Boolean functions. We previously developed a Boolean expression manipulator, that can quickly calculate Boolean expressions by using BDD techniques. It has greatly assisted us in developing VLSI design systems and solving combinatorial problems. In this paper, we present an Arithmetic Boolean Expression Manipulator (BEM-II), that is also based on BDD techniques. BEM-II calculates Boolean expressions that contain arithmetic operations, such as addition, subtraction, multiplication and comparison, and then displays the results in various formats. It can solve problems represented by a set of equalities and inequalities, which are dealt with in 0-1 linear programming. We discuss the algorithm and data structure used for manipulating arithmetic Boolean expressions and show the formats used for displaying the results. The specifications for BEM-II are described and several application examples are presented. Arithmetic Boolean expressions will be useful for various applications. They perform well in terms of the total time for programming and execution. We expect BEM-II to facilitate research and development of digital systems.

An enhanced computer networks course

In order to enhance students' training in computer systems, the Ministry of Education (MoE) of the Republic of China (ROC) in Taiwan area has provided NT$50,000,000 (about US$2,000,000) to support the computer system education enhancement project in 1992-1993. This project purely emphasizes the system aspect of computer science education. Seven types of computer science- and information-oriented courses are taken into consideration: programming languages and compilers, operating systems and system programming, computer architectures and VLSI design, databases and file systems, computer networks, I/O systems, and software engineering, teachers from all universities in Taiwan area are all encouraged to propose their enhanced courses. The MoE's grant is allowed to purchase some hardware and software facilities, to support two teaching assistants (TAs), and to have some miscellaneous expenses, e.g., disks, tapes, toner, Xerox charge, etc., for each granted course. This paper presents an enhanced course in computer networks that was taught by the author and was granted by the above project. >

A VLSI design system for teaching introduction to microelectronics

A set of software tools currently used for teaching a course on introduction to VLSI design to graduate and undergraduate students at Osaka University (Japan), the University of Toulouse (France), and the Polytechnical University of Barcelona (Spain), is described. The system includes tools such as schematic capture, mask-level design, and mix-mode simulation. Specific tools such as logic and analog simulation, three-dimensional process simulation, and CMOS logic cell compiler are also included in the software, which represents a valuable educational environment successfully used by a large number of students. The authors present an overview of the complete tool set, essential matters about MOS devices, and the CMOS process. They detail the techniques used for logic design, mask-level design, and mix-mode simulation. They discuss the interest of using such tools in such a course.< <ETX xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">&gt;</ETX>

A general-purpose framework for CAD algorithms

The demands imposed by large circuits on computer-aided design (CAD) systems are discussed, showing how each can be met. In particular, it is shown how a CAD system can handle many tools, accommodation different design environments, provide a flexible interface, provide user-specified constraints, and be platform independent. A complete system, called the Electric VLSI Design System which exhibits all of these features is described.< <ETX xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">&gt;</ETX>

An information management system for engineering design based on hypertext

This article presents the results of an investigation which should clarify whether it is feasible to use a hypertext system for the data management of a VLSI design system. A short introduction into the Electronic Design Interchange Format (EDIF) is given, as the hypertext schema for design data is based on EDIF. The main issues of the hypertext paradigm are reviewed, and the HyperEDIF system is presented. HyperEDIF is based on a commercially available hypertext system and contains a schema for the management of VLSI design data. The knowledge gained during the development of this system is also reported. The consequential demands placed on a hypertext system to be used for design data management are discussed in detail.

A Smalltalk/V VLSI CAD application

The purpose of the work described was to explore the utility of the Smalltalk/V object-oriented language in prototyping an application that would form just one module of a potentially much more extensive and complex system, a complete VLSI design system. The author also wanted to investigate issues arising from the fact that the application itself and the development methodology would have to anticipate the integration of a series of processes that would extend both up- and downstream; for example, logical and functional design stages, circuit synthesis and testing etc. Others have applied OOP to logic circuit design and to logic simulation. Here OOP is applied to the physical layout of the mask-level geometrical entities that go to make up the silicon realisation of an IC design. >

GENESIS—A Standard Cell Based VLSI Design System

This paper describes GENESIS, a Standard Cell based VLSI Design System. GENESIS was designed to be used on simple, slow machines such as IBM-PCs with little memory and low resolution graphics, though additional hardware can be used if available. Implementing a complete design system on these machines imposes servere constraints, particularly for interactive programs where response time is crucial. GENESIS consists of two sets of modules—one for designing a Cell Library, and another for designing chips (systems) using library cells. GENESIS has many original algorithms incorporated in it, including a new circuit extraction strategy, and original algorithms for placement, global routing and channel routing. It is being used as a teaching aid for graduate and undergraduate students in VLSI design courses at the Indian Institute of Technology, Delhi. The modular nature of GENESIS makes it useful as a vehicle for developing and testing new algorithms in a design environment. It also makes it facile to link new modules with it. A Systolic arrary compiler has been linked with GENESIS, enabling chips implementing a systolic algorithm specified by the user to be compiled.

LES: a layout expert system

The LES expert system for layout generation of random logic modules in a hierarchical CMOS VLSI design system is described. It applies a combination of rule- and algorithmic-based techniques on a novel layout style. The layout style utilizes silicon area more efficiently than a previously developed style. Experimental results have demonstrated the superiority of this expert system against various standard-cell systems and its competitiveness with human designers. >

The VIVID Symbolic Design System: Current Overview And Future Directions

VIVID, the vertically integrated VLSI design system developed at the Microelectronics Center of North Carolina, was first released in January 1985. Since that time feedback from wide industrial and academic exposure has been positive, confirming the need for symbolic design tools and providing research and development insignts?illuminating insights that should also be of interest to the CAD community. Coining a line from Robert Burns poem ?To a Mouse,? the best-laid plans of mice and software designers are not always implemented. When examining the data, assumptions, and analyses that motivated VIVID, one discovers planned (but discarded) developments; however, an inclusive overvoew is needed to properly evaluate those data, assumptions, and analyses. Knowing clearly why something was done and how it fits into the overall picture can help us to frame future decisions and shape future designs.

A Database-Driven VLSI Design System

We describe an effort in applying database technology to the VLSI design process. By mixing software tools, relational database concepts, sophisticated index management, and existing VLSI design tools, we have built a flexible, interactive VLSI design system that provides data independence and technology independence. Design tools are interfaced with a centralized database to form an integrated design environment.

A synthesis system for PLA-based programmable hardware

An automatic synthesis system for PLA based programmable hardware as part of a VLSI design system is presented. In order to reduce the needed silicon area of a PLA implementation we suggest algorithms for segmentation, term minimization and PLA — folding. We present results of the implemented term minimization and PLA-folding procedures.

Color-mapping techniques for computer-aided design and verification of VLSI systems

Color raster-scan displays are often equipped with hardware for color transformation. Because the transformation can be redefined much more quickly than a full image can be computed (in a host) and subsequently displayed, it is preferable when possible to perform image operations by simply changing the mapping. Here an interactive layout system for NMOS VLSI is described which gives immediate feedback in color. Viewing modes are emphasized; opaque and translucent modes are discussed which allow the flexibility required for efficient understanding of the design by the designer. The color table is also used to help the designer detect violations of design rules; design rule violations can be readily detected when the transformation unit is used to highlight overlaps of selected VLSI layers or fringe structures derived from them. These color-mapping methods for man-machine interaction promise to enhance the productivity of the designer considerably, and they point the way to VLSI design systems of the future.