CMOS VLSI Implementation Research Articles

CMOS VLSI Implementation of Adders with Low Leakage Power

CMOS VLSI Implementation of Adders with Low Leakage Power

VLSI architecture for 4-D depth filtering

We propose the application of light field cameras and depth-selective 4-D IIR filtering to enable video surveillance, leveraging the post-capture depth-selective filtering enabled by computational photography. Novel ultralow-complexity differential-form depth-selective 4-D IIR filter algorithms and their corresponding architectures are proposed for processing 4-D light fields. Practical results are presented for real-world video sequences, and a CMOS VLSI implementation of the arithmetic processing elements is synthesized. The architecture shows \(86.66\), \(78.94\,\%\) reduction in multipliers and adders compared to direct-form structure and delivers 26 frames/s for light fields of size \(16\times 16\times 128\times 128\).

Evaluation of Power Constant Dual-Rail Logics Countermeasures against DPA with Design Time Security Metrics

Cryptographic circuits are nowadays subject to attacks that no longer focus on the algorithm but rather on its physical implementation. Attacks exploiting information leaked by the hardware implementation are called side-channel attacks (SCAs). Among these attacks, the differential power analysis (DPA) established by Paul Kocher et al. in 1998 represents a serious threat for CMOS VLSI implementations. Different countermeasures that aim at reducing the information leaked by the power consumption have been published. Some of these countermeasures use sophisticated back-end-level constraints to increase their strength. As suggested by some preliminary works (e.g., by Li from Cambridge University), the prediction of the actual security level of such countermeasures remains an open research area. This paper tackles this issue on the example of the AES SubBytes primitive. Thirteen implementations of SubBytes, in unprotected, WDDL, and SecLib logic styles with various back-end-level arrangements are studied. Based on simulation and experimental results, we observe that static evaluations on extracted netlists are not relevant to classify variants of a countermeasure. Instead, we conclude that the fine-grained timing behavior is the main reason for security weaknesses. In this respect, we prove that SecLib, immune to early-evaluation problems, is much more resistant against DPA than WDDL.

Freeman olfactory cortex model: A multiplexed KII network implementation

This paper presents the results of a CMOS-VLSI implementation of a realistic computational model proposed by Walter Freeman for the olfactory system. This model, in later years, has been studied for engineering applications such as auto-association and classification. The analogue nature of the model motivates analogue VLSI implementations. However, the dimension and complexity of such system poses many obstacles to an analogue electronic implementation; one such is the massive interconnectivity which size increases with the square of the number of inputs (channels). We suggest a multiplexing procedure that puts the burden of interconnectivity over a digital system that is simpler to design and makes the analogue system more treatable. The procedure naturally samples the signals. To avoid smoothing filters, a discrete-time solution was also employed. Although with such approach the time resolution is reduced, the advantages overcome the detriments. Previous work has shown that the model can be efficiently discretized using DSP techniques, resulting on a system that is able to predict, on sample-by-sample basis, the behaviour of the VLSI circuit, allowing for a simple and flexible way to adjust the circuit parameters. We present the measured circuit results that are further confronted with the digital implementation.

Programmable analogue VLSI implementation for asymmetric sigmoid neural activation function and its derivative

A new CMOS VLSI implementation of an asymmetric programmable sigmoid neural activation function, as well as of its derivative, is presented. It consists of two coupled PMOS and NMOS differential pairs with different programmable bias currents that set the upper and lower limits of the sigmoid. The circuit works in the weak inversion region, for low power consumption and exponential envelope, or in strong inversion to achieve higher speeds. The results obtained from the theoretical transfer function, and from the simulations of the circuit implemented in AMI's 0.35 µm technology, show a very good match.

ORIENTED SPATIAL PATTERN FORMATION IN A FOUR LAYER CMOS CELLULAR NEURAL NETWORK

Cellular neural networks have found applications both as a platform for high speed image processing, as well as a model for complex spatiotemporal dynamical phenomena. This paper describes spatial pattern formation in a CMOS VLSI implementation of a CNN. With four layers of 32×64 cells, this CNN contains the most recurrently interconnected 2D layers of any VLSI CNN implementation to date. With over 8000 cells, it is also one of the largest in terms of the total number of cells. The spatial patterns generated by this network are bands of activity with a preferred scale and orientation, both of which can be adjusted via external bias voltages. The VLSI implementation provides a physical substrate for experimenting with complex spatiotemporal phenomena in real time, while also being amenable to theoretical analysis. Our experimental characterization of the observed patterns are in excellent agreement with our theoretical predictions.

Cmos vlsi implementation of a low-power logarithmic converter

We present a unique 32-bit binary-to-binary logarithm converter including its CMOS VLSI implementation. The converter is implemented using combinational logic only and it calculates a logarithm approximation in a single clock cycle. Unlike other complex logarithm correcting algorithms, three unique algorithms are developed and implemented with low-power and fast circuits that reduce the maximum percent errors that result from binary-to-binary logarithm conversion to 0.9299 percent, 0.4314 percent, and 0.1538 percent. Fast 4, 16, and 32-bit leading-one detector circuits are designed to obtain the leading-one position of an input binary word. A 32-word/spl times/5-bit MOS ROM is used to provide 5-bit integers based on the corresponding leading-one position. Both converter area and speed have been considered in the design approach, resulting in the use of a very efficient 32-bit logarithmic shifter in the 32-bit logarithmic converter. The converter is implemented using 0.6/spl mu/m CMOS technology, and it requires 1,600/spl lambda//spl times/2,800/spl lambda/ of chip area. Simulations of the CMOS design for the 32-bit logarithmic converter, operating at V/sub DD/ equal to 5 volts, run at 55 MHz, and the converter consumes 20 milliwatts.

A VLSI crossbar switch with wrapped wave front arbitration

Crossbar switch is a key component of communication switches used in networks. Allocation of resources has a direct impact on packet transmission. A poor allocation results in long transmission delays. Hence, switches must include an arbiter that efficiently allocates the crossbar's resources. In this brief, a novel VLSI CMOS implementation of a high performance wrapped wave front arbitration (WWFA) for crossbar switches is described. Arbitration time is one of the critical factors that affect network performance. WWFA requires a two-dimensional arbitration that incorporates a rotating priority to provide fair arbitration. In this brief, we describe the design and implementation of this arbiter. The arbiter is capable of performing an arbitration in 1.15 ns using 0.5-/spl mu/m technology, for a 4 /spl times/ 4 crossbar. We also include the description of interface and crosspoint (CP) control circuitry, i.e., request-acknowledge circuit and CP controller circuit respectively.

Focal Plane Implementation of 2D Steerable and Scalable Gabor-Type Filters

We describe the analog CMOS VLSI implementation of a cellular neural network (CNN) architecture which spatially filters a 2D image by two orientation selective image filters. The image is represented by a set of input currents supplied by an on-chip array of photosensors. The filters are similar to even and odd Gabor filters. The CNN architecture is implemented using two resistive networks coupled by transconductance amplifiers. The tuned orientation can be steered and the filter response scaled by adjusting the conductances of the resistors and gains of the transconductance amplifiers through externally supplied bias voltages. The circuit operation is explained via a variational principle, which defines the filter output as the minimum of a cost function. We report test results from both 25 × 25 and 45 × 45 pixel arrays.

VLSI design for high-speed LZ-based data compression

A simple real-time parallel architecture for CMOS VLSI implementation of a Ziv–Lempel data compression system is presented. This encoding system employs a linear systolic array to find concurrently the matches between each input data character and its corresponding dictionary, and can easily achieve ideal compression ratio by cascading the chips of the encoding cell. A new encoding architecture is proposed to improve the encoding speed and reduce hardware complexity for the encoding cells. In addition, the number of memory accesses is reduced to save power consumption for high-speed applications. The encoder codes one character (more than eight bits) per encoding cycle. The clock rate by Verilog simulator can be constrained below 15 ns using the Compass standard cell library for the 0.6 µm CMOS process.

Hazard-Free Self-Timed Design: Methodology and Application to Asynchronous Routing in an Heterogeneous Parallel Machine

The goal of this research is to enable the actual building of parallel machines. The example chosen in this paper is a heterogeneous parallel machine with an intrinsic asynchronous behavior. An asynchronous router fully supports such a logical asynchronism. However, every parallel processor would exhibit asynchronism similar enough to warrant the study of a general methodology. The main part of the paper deals with an original method that ensures a hazard-free self-timed design assuming the worst conditions for robustness. Hazards are classified under three types. On top of logic hazards that resort to implementation, equation hazards are eliminated by an optimal covering. A new variable labelled state-trajectory is proposed: its integrity guarantees immunity to function hazards. The method was fruitfully applied to the VLSI CMOS implementation of the above-mentioned router. Peculiar fully customized cells were designed. Circuit-measured performances as well as some machine inner-communication performances are presented.

An automatic gain control architecture for SONET OC-3 VLSI

This work presents a synchronized feedback-type automatic gain control (AGC) architecture for SONET (synchronous optical network) OC-3 system which is suitable for scaled BJT or CMOS VLSI implementation. In this architecture, a second-order loop is utilized instead of a conventional loop, and a convenient methodology is presented for calculating the parameters of the AGC. Simulation results using micromodels in the HSPICE environment indicate that for a 20 dB dynamic range of input 77.76 MHz sinusoidal signal, the architecture yields an 80 kHz loop bandwidth and a constant 1 V/sub pp/ output magnitude.

A new neural network for solving linear programming problems

We propose and analyse a new class of neural network models for solving linear programming (LP) problems in real time. We introduce a novel energy function that transforms linear programming into a system of nonlinear differential equations. This system of differential equations can be solved on-line by a simplified low-cost analog neural network containing only one single artificial neuron with adaptive synaptic weights. The network architecture is suitable for currently available CMOS VLSI implementations. An important feature of the proposed neural network architecture is its flexibility and universality. The correctness and performance of the proposed neural network is illustrated by extensive computer simulation experiments.

Scarce-state-transition syndrome-former error-trellis decoding of (n,n-1) convolutional codes

A novel scarce-state-transition (SST) type trellis decoding system for (n,n-1) convolutional codes with coherent BPSK signals is proposed. The new system retains the same number of binary comparisons as the syndrome-former trellis decoding technique. Like the original SST-type encoder trellis technique, the proposed system is also suitable for CMOS VLSI implementation. A combination of the two techniques results in a less complex and low power consumption decoding system.

VLSI implementation of locally connected neural network for solving partial differential equations

This brief presents a locally connected neural network for solving a class of partial differential equations. Each neural cell is designed using active and passive components. An architecture is described to control the weights between the neurons. The major benefit of the architecture is that it does not require additional space outside of the cell for routing the control lines no matter how many cells are used. The CMOS VLSI implementation of a sixteen cell network was fabricated and measured. The results of this network are compared to the numerical solution of the partial differential equations.

Scarce-state-transition error-trellis decoding ofblock codes with BPSK signals

A novel decoding technique for linear block codes with coherent BPSK signals is proposed. The new system has the same error performance as and similar complexity to the conventional trellis decoding of block codes. Like the scarce-state-transition Viterbi decoding of convolutional codes , the proposed system is also well suited for CMOS VLSI implementation and has a lower power consumption.

Winner-take-all neural network and its application to minimax optimisation problems

A new and simple winner-take-all neural subnetwork suitable for VLSI CMOS implementation is proposed. The subnetwork is used for the real-time solving of minimax optimisation problems. In particular, the Letter shows how to solve, in real time, an over-determined system of linear equations by using the Chebyshev L∞ norm criterion and a neural network approach. The validity and performance of the network have been checked by extensive computer simulation of different minimax optimisation problems.

Switching integrated broadband services by sort-banyan networks

Substantial attention has recently been given to the implementation of sort-banyan networks for switching asynchronous transfer mode (ATM) transmission links in a BISDN (broadband integrated service digital network) network. The author gives a three-dimensional view of the theory and implementation of switching, as well as variations of the basic scheme. ATM switches are classified as blocking versus nonblocking, unicast versus multicast, and input queued versus output queued. Sorting networks structured by a three-dimensional interconnection topology are studied. A sorting network, when coupled with a banyan routing network structured in three dimensions, becomes a self-routing and nonblocking switching network. This three-dimensional topology allows CMOS VLSI implementations of the subnetworks and interconnection of these subnetworks at a speed of 150 Mb/s and beyond. The sorting mechanism can also be used for output conflict resolution, subsequently making the switch suitable for ATM switching. Recent enhancements, which provide features such as parallelism, trunk grouping, and modularity, are also described. These features enhance the throughput/delay performance, provide better fault and synchronization tolerance, and enable more economical growth for switch size.< <ETX xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">&gt;</ETX>

VLSI implementation of a 16-state coset code

Calderbank and Sloane [1] have recently introduced a new technique for constructing trellis codes based on lattices and cosets. Codes based on these principles will be referred to in this paper as coset codes. We present a parallel 2μ CMOS VLSI implementation of a particular 16-state coset code described in [1]. The encoder decoder for this code were developed using Path-Programmable Logic (PPL) design methodology [6]. The resulting system occupies four chips and should be able to operate at data rates approaching 50 megabits per second. An alternative design using 1μ CMOS technology could be implemented on two chips and could operate at data rates up to 100 megabits per second.

Speech preprocessing using analog VLSI

The aim of this project is analog CMOS VLSI implementation of a low‐power, real‐time front‐end processor for speech recognition and for multichannel aids for the deaf. Physiological studies of the mammalian auditory periphery indicate that synchrony coding of speech signals by the temporal pattern of activity in the auditory nerve is noise resistant and performs amplitude compression without distortion over a wide range [M. B. Sachs, H. F. Voigt, and E. D. Young, J. Neurophysiol. 50, 27–45 (1983)]. In a number of studies using digital computation to model the auditory periphery, the properties of synchrony coding of speech signals have been explored [K. L. Payton, J. Acoust. Soc. Am. 83, 145–162 (1988), and articles in J. Phonet. 16, 1 (1988)]. Here VLSI realization of the middle ear, the basilar membrane, and the hair cell and synapse are presented along with design features of the analog VLSI approach. The multichannel outputs correspond to the time‐varying firing rates of neurons from discrete places o...