VLIW Research Articles

Complementing software pipelining with software thread integration

Software pipelining is a critical optimization for producing efficient code for VLIW/EPIC and superscalar processors in high-performance embedded applications such as digital signal processing. Software thread integration (STI) can often improve the performance of looping code in cases where software pipelining performs poorly or fails. This paper examines both situations, presenting methods to determine what and when to integrate.We evaluate our methods on C-language image and digital signal processing libraries and synthetic loop kernels. We compile them for a very long instruction word (VLIW) digital signal processor (DSP) -- the Texas Instruments (TI) C64x architecture. Loops which benefit little from software pipelining (SWP-Poor) speed up by 26% (harmonic mean, HM). Loops for which software pipelining fails (SWP-Fail) due to conditionals and calls speed up by 16% (HM). Combining SWP-Good and SWP-Poor loops leads to a speedup of 55% (HM).

PLX: An Instruction Set Architecture and Testbed for Multimedia Information Processing

PLX is a concise instruction set architecture (ISA) that combines the most useful features from previous generations of multimedia instruction sets with newer ISA features for high-performance, low-cost multimedia information processing. Unlike previous multimedia instruction sets, PLX is not added onto a base processor ISA, but designed from the beginning as a standalone processor architecture optimized for media processing. Its design goals are high performance multimedia processing, general-purpose programmability to support an ever-growing range of applications, simplicity for constrained environments where low power and low cost are paramount, and scalability for higher performance in less constrained multimedia systems. Another design goal of PLX is to facilitate exploration and evaluation of novel techniques in instruction set architecture, microarchitecture, arithmetic, VLSI implementations, compiler optimizations, and parallel algorithm design for new computing paradigms. Key characteristics of PLX are a fully subword-parallel architecture with novel features like wordsize scalability from 32-bit to 128-bit words, a new definition of predication, and an innovative set of subword permutation instructions. We demonstrate the use and high performance of PLX on some frequently-used code kernels selected from image, video, and graphics processing applications: discrete cosine transform, pixel padding, clip test, and median filter. Our results show that a 64-bit PLX processor achieves significant speedups over a basic 64-bit RISC processor and over IA-32 processors with MMX and SSE multimedia extensions. Using PLX's wordsize scalability feature, PLX-128 often provides an additional 2× speedup over PLX-64 in a cost-effective way. Superscalar or VLIW (Very Long Instruction Word) PLX implementations can also add additional performance through inter-instruction, rather than intra-instruction parallelism. We also describe the PLX testbed and its software tools for architecture and related research.

Application specific instruction-set processor template for motion estimation in video applications

The gap between application specific integrated circuits (ASICs) and general-purpose programmable processors in terms of performance, power, cost and flexibility is well known. Application specific instruction-set processors (ASIPs) bridge this gap. In this work, we demonstrate the key benefits of ASIPs for several video applications. One of the most compute- and memory-intensive functions in video processing is motion estimation (ME). The focus of this work is on the design of a ME template, which is useful for several video applications like video encoding, obstacle detection, picturerate up-conversion, 2-D-to-3-D video conversion, etc. An instruction-set suitable for performing a variety of ME functions is developed. The ASIP is based on a very long instruction word (VLIW) processor template and meets low-power and low-cost requirements still providing the flexibility needed for the application domain. The ME ASIP design consumes 27 mW and takes an area of 1.1 mm/sup 2/ in 0.13 /spl mu/m technology performing picturerate up-conversion, for standard definition (CCIR601) resolution at 50 frames per second.

Reducing the complexity of instruction-level power models for VLIW processors

Aim of this paper is to propose a high-level power exploration framework based on an instruction-level energy model for VLIW (Very Long Instruction Word) architectures. More specifically, the present paper deals with the reduction of the complexity of the energy model of K-issue VLIW processors from exponential with respect to the number of operations within the Instruction Set O(?ISA? K ) to quadratic (O(K*?ISA?2)). The complexity of the energy model has been further simplified by automatically clustering the operations in the ISA with respect to their average energy. Globally, the proposed approach reduces the complexity of the characterization problem for a K-issue VLIW processor to quadratic (O(K*?C?2)) with respect to the number of operation clusters. In this way, a more efficient characterization of the VLIW core power consumption can been achieved, while preserving the accuracy of the power estimates. The proposed model has been further extended to provide early power figures and energy/performance trade-offs for multi-cluster VLIW architectures composed of multiple data-path units and a single instruction cache control unit. The proposed high-level power estimation methodology has been applied to the Lx 4-issue VLIW pipelined processor provided by STMicroelectronics.

Leakage-aware compilation for VLIW architectures

Power consumption has been widely recognised as the most important design limiter for continued increase in the number of transistors integrated into a chip. Specifically, static power consumption has emerged as a significant concern in newer technologies with smaller threshold voltages and feature sizes. Addressing this important challenge requires solutions at different levels of a chip design, ranging from improvements in fabrication process to energy-aware software design. The paper shows how a compiler can play an important role in reducing the leakage power consumption. The strategy is built upon a data-flow analysis that identifies basic blocks that do not use a given functional unit. Collecting this information from all basic blocks in the code, it then inserts activate/deactivate instructions in the code to set/reset a sleep signal which controls leakage current of functional units. To evaluate the effectiveness of their strategy, the authors implemented different versions of it using an experimental compiler and simulation environment and conducted experiments using a VLIW (very long instruction word) architecture and several media applications as well as array-intensive codes. Their experimental results show that the proposed compiler-based strategy is very effective in reducing leakage energy of functional units.

Low-power branch prediction techniques for VLIW architectures: a compiler-hints based approach

The paper introduces a dynamic branch prediction scheme suitable for energy-aware Very Long Instruction Word (VLIW) processors. The proposed technique is based on a compiler hint mechanism to filter the accesses to the branch predictor blocks. We define a configurable hint instruction which anticipates some static information about the upcoming branch to reduce the hardware involved in the prediction, thus, the energy consumption. To analyze the effectiveness of the proposed low-power branch prediction scheme, we combined it with some well-known dynamic branch prediction techniques suitable for VLIW processors. The analyzed branch predictors are characterized by simple hardware implementations, matching the low-power characteristics of the target VLIW processors. Experimental results have been carried out on Lx, an industrial 4-issue VLIW architecture.

A scalable instruction buffer and align unit for xDSPcore

Increasing mask costs and decreasing feature sizes together with productivity demand have led to the trend of platform design. Software programmable embedded cores are used to provide the necessary flexibility in integrated systems. Facing increasing system complexity, single-issue digital signal processors (DSPs) have been replaced by cores providing the execution of several instructions in parallel. The most common programming model for multi-issue DSP core architectures is Very Long Instruction Word (VLIW) which is based on static scheduling, and enables minimization of the worst case execution time and reduces core complexity. The drawback of traditional VLIW is poor code density, which leads to high program memory requirements and, therefore, requires a large silicon area of the DSP subsystem. To overcome this problem without limiting the core performance, a scalable long instruction word (xLIW) is introduced. A special align unit is used for implementing the xLIW program memory interface. In this paper, the align unit and its main architectural feature, a scalable instruction buffer, is introduced in detail. xLIW is part of a project for a parameterized DSP core.

Combined Application of Data Transfer and Storage Optimizing Transformations and Subword Parallelism Exploitation for Power Consumption and Execution Time Reduction in VLIW Multimedia Processors

In this paper the important issues in mapping data dominated multimedia applications on Very Long Instruction Word (VLIW) multimedia processors are addressed. The main design quality factors of applications realized on the target architecture platform are presented and their interactions are explored. Power consumption is the major cost factor while performance is the overriding constraint in realizations of multimedia applications on the target architecture platform. A methodology for the reduction of the data transfer and storage related power consumption, which forms an important part of the total power budget of the system, and the execution time of applications realized on VLIW multimedia processors, has been developed. The methodology is based on the application of a number of transformations, mainly oriented towards data transfer and storage optimization, to a high level description of the target application. The main focus of this paper is on the interaction of the proposed code transformations with the exploitation of subword parallelism (for example through the application of special performance improving arithmetic subword instructions present in modern VLIW multimedia processors). Experimental results from real-life data-dominated multimedia applications clearly demonstrate that the application of the proposed transformations is orthogonal to the exploitation of subword parallelism. A second conclusion is that the positive impact of the proposed code transformations on performance is typically even larger than the effect of the subword parallelism exploitation for the complete application. The effect of the subword parallelism exploitation is even enhanced after the application of the proposed code transformations.

Code optimizations for a VLIW‐style network processing unit

AbstractThe explosive growth in network bandwidth and Internet services such as QoS (quality of service) and SLA (service level agreement) monitoring have created the need for new networking hardware called a Network Processing Unit (NPU). In order to rapidly reconfigure the NPU for frequently varying Internet services and technologies, a high‐performance C compiler is urgently needed. Several code generation techniques, which are intended to meet the high code quality demands of other types of application specific instruction‐set processors (ASIPs) like digital signal processors (DSPs), have already been developed. However, these techniques are insufficient for NPUs due to striking architectural differences such as asymmetric data paths. The main purpose of this paper is to discuss our recent experience with the development of a commercial compiler for a new NPU called the Paion PPII, which is basically a packet engine for NPU to meet the growing need for new high‐bandwidth communication equipment targeted for Internet routers and ethernet adapters. For this purpose, we will first show the architectural challenges posed by the target NPU. Then, we will describe several compiler techniques that we found to be effective for the target NPU with various unorthogonal architectural features. The current implementations of the PPII use a VLIW (Very Long Instruction Word) architecture. So, we handled this VLIW‐style architecture by employing a simple code compaction scheme which packs multiple parallel instructions into one long instruction word. The experimental results show that our techniques are effective for significantly reducing the dynamic instruction count. Copyright © 2004 John Wiley & Sons, Ltd.

Software pipelining

The basic idea behind software pipelining was first developed by Patel and Davidson for scheduling hardware pipe-lines. As instruction-level parallelism made its way into general-purpose computing, it became necessary to automate scheduling. How and whether instructions can be scheduled statically have major ramifications on the design of computer architectures. Rau and Glaeser were the first to use software pipelining in a compiler for a machine with specialized hardware designed to support software pipelining. In the meantime, trace scheduling was touted to be the scheduling technique of choice for VLIW (Very Long Instruction Word) machines. The most important contribution from this paper is to show that software pipelining is effective on VLIW machines without complicated hardware support. Our understanding of software pipelining subsequently deepened with the work of many others. And today, software pipelining is used in all advanced compilers for machines with instruction-level parallelism, none of which, except the Intel Itanium, relies on any specialized support for software pipelining.This paper shows that software pipelining is an effective and viable scheduling technique for VLIW processors. In software pipelining, iterations of a loop in the source program are continuously initiated at constant intervals, before the preceding iterations complete. The advantage of software pipelining is that optimal performance can be achieved with compact object code.This paper extends previous results of software pipelining in two ways: First, this paper shows that by using an improved algorithm, near-optimal performance can be obtained without specialized hardware. Second, we propose a hierarchical reduction scheme whereby entire control constructs are reduced to an object similar to an operation in a basic block. With this scheme, all innermost loops, including those containing conditional statements, can be software pipelined. It also diminishes the start-up cost of loops with small number of iterations. Hierarchical reduction complements the software pipelining technique, permitting a consistent performance improvement be obtained.The techniques proposed have been validated by an implementation of a compiler for Warp, a systolic array consisting of 10 VLIW processors. This compiler has been used for developing a large number of applications in the areas of image, signal and scientific processing.

Algorithms and analysis of scheduling for low-power high-performance DSP on VLIW processors

Switching activity and schedule length are the two most important factors that influence the energy consumption of an application executed on a VLIW (very long instruction word) processor. Considering these two factors together, we propose an instruction-level energy-minimisation scheduling technique to reduce the energy consumption of applications on VLIW processors. We first formally prove that this problem is NP-complete. Then three heuristic algorithms, MSAS, MLMSA, and EMSA, are proposed. While switching activity and schedule length are given higher priority in MSAS and MLMSA respectively, EMSA gives the best result considering both of them. The experimental results show that EMSA gives a 31.7% reduction in energy compared with the traditional list scheduling approach on average.

A low-cost media-processor based real-time MPEG-4 video decoder

Due to the high-sped development in semiconductor technology, general-purpose computers can process digital video, audio and graphics easily. Nowadays, the similar functionality has shifted from the general-purpose computer to the so-called media-processor one. Since the processor is targeted on mass-produced consumer electronic devices, the price and the ease of use are the main concern. The latest MPEG-4 video coding standard, which consumes relatively low bit-rate but yields acceptable quality, meets the target exactly. In this paper, by realizing an MPEG-4 codec using both general-purpose processor and media-processor, we investigated some issues related to the use of a media-processor for satisfying various multimedia compression and processing requirements. The investigated issues include the speedup of the MPEG-4 decoder based on a media-processor DSP chip, a multimedia co-processor or hardware accelerator, the very long instruction word (VLIW) and the single instruction multiple data stream (SIMD) programming techniques. Moreover, a media-processor based MPEG-4 solution for set-top box application is also included.

A VLIW processor with reconfigurable instruction set for embedded applications

This paper describes a new architecture for embedded reconfigurable computing, based on a very-long instruction word (VLIW) processor enhanced with an additional run-time configurable datapath. The reconfigurable unit is tightly coupled with the processor, featuring an application-specific instruction-set extension. Mapping computation intensive algorithmic portions on the reconfigurable unit allows a more efficient elaboration, thus leading to an improvement in both timing performance and power consumption. A test chip has been implemented in a standard 0.18-μm CMOS technology. The test of a signal processing algorithmic benchmark showed speedups ranging from 4.3× to 13.5× and energy consumption reduced up to 92%.

A constant-quality, single-pass VBR control for DVD recorders

This paper describes a low complexity variable bit-rate (VBR) control method that achieves excellent and constant visual quality for single-pass, real time MPEG-2 encoding in DVD recorders. The bit-rate is controlled in a very accurate way. The algorithm runs in software on a very long instruction word (VLIW) processor by using less than 3 Millions of clock cycles.

A statistical adaptive block-matching motion estimation

We address the problem of motion estimation (ME) in digital video sequences and propose a new fast, adaptive, and efficient block-matching algorithm. Higher quality and efficiency are achieved using a statistical model for the motion vectors. This model introduces adaptation in the search window, drastically reducing the number of positions where correlation-type computation is performed. The efficiency is further improved by progressively undersampling the macroblock. Patterns for undersampling are proposed to obtain the maximum benefit from single instruction multiple data (SIMD) instructions. In contrast with existing motion-estimation techniques, search strategy and subsampled patterns are closely linked. This shows that a good search strategy is much more important than blindly reducing the number of pixels considered for the matching pattern. We describe an implementation of the proposed matching strategy that exploits the very long instruction word (VLIW) and SIMD technology available in the new Itanium processor family. Results show that the proposed algorithm adapts easily to the evolution of the scene avoiding annoying quality drops that can be observed with other deterministic algorithms. The total number of operations required by the proposed method is inferior to those required by traditional approaches.

Division of Labor in Embedded Systems

Increasingly, embedded applications require more processing power than can be supplied by a single processor, even a heavily pipelined one that uses a high-performance architecture such as very long instruction word (VLIW) or superscalar. Simply driving up the clock is often prohibitive in the embedded world because higher clocks require proportionally more power, a commodity often scarce in embedded systems. Multiprocessing, where the application is run on two or more processors concurrently, is the natural route to ever more processor cycles within a fixed power budget.

Using Graph Models in Retargetable Optimizing Compilers for Microprocessors with VLIW Architectures

A mathematical model of programs, which is based on the concept of a hierarchical graph, is described. The model is used in the retargetable optimizing compiler NVRK-2 for microprocessor architectures with irregular very long instruction words (VLIWs). A formal description of a microprocessor with such an architecture is proposed and issues of code generation and analysis of microprocessors with VLIWs extended by a collection of instructions for signal processing and multimedia application are discussed. The problem of the computational speedup of the architectures being considered is also discussed.

Low-power data forwarding for VLIW embedded architectures

Proposes a low-power approach to the design of embedded very long instruction word (VLIW) processor architectures based on the forwarding (or bypassing) hardware, which provides operands from interstage pipeline registers directly to the inputs of the function units. The power optimization technique exploits the forwarding paths to avoid the power cost of writing/reading short-lived variables to/from the register file (RF). Such optimization is justified by the fact that, in application-specific embedded systems, a significant number of variables are short-lived, that is, their liveness (from first definition to last use) spans only few instructions. Values of short-lived variables can thus be accessed directly through the forwarding registers, avoiding writeback to the RF by the producer instruction and successive read from the RF by the consumer instruction. The decision concerning the enabling of the RF writeback phase is taken at compile time by the compiler static scheduling algorithm. This approach implies a minimal overhead on the complexity of the processor control logic and, thus, no critical path increase. The application of the proposed solution to a VLIW embedded core has shown an average RF power saving of 7.8% with respect to the unoptimized approach on the given set of target benchmarks.

An instruction-level energy model for embedded VLIW architectures

In this paper, an instruction-level energy model is proposed for the data-path of very long instruction word (VLIW) pipelined processors that can be used to provide accurate power consumption information during either an instruction-level simulation or power-oriented scheduling at compile time. The analytical model takes into account several software-level parameters (such as instruction ordering, pipeline stall probability, and instruction cache miss probability) as well as microarchitectural-level ones (such as pipeline stage power consumption per instruction) providing an efficient pipeline-aware instruction-level power estimation, whose accuracy is very close to those given by RT or gate-level simulations. The problem of instruction-level power characterization of a K-issue VLIW processor is O(N/sup 2K/) where N is the number of operations in the ISA and K is the number of parallel instructions composing the very long instruction. One of the advantages of the proposed model consists of reducing the complexity of the characterization problem to O(K/spl times/N/sup 2/). The proposed model has been used to characterize a four-issue VLIW core with a six-stage pipeline.

Architectural differences of efficient sequential and parallel computers

In this paper we try to conclude what kind of a computer architecture is efficient for executing sequential problems, and what kind of an architecture is efficient for executing parallel problems from the processor architect's point of view. For that purpose we analytically evaluate the performance of eight general purpose processor architectures representing widely both commercial and scientific processor designs in both single processor and multiprocessor setups. The results are interesting. The most efficient architecture for sequential problems is a two-level pipelined VLIW (very long instruction word) architecture with few parallel functional units. The most efficient architecture for parallel problems is a deeply inter-thread superpipelined architecture in which functional units are chained. Thus, designing a computer for efficient sequential computation leads to a very different architecture than designing one for efficient parallel computation and there exists no single optimal architecture for general purpose computation.