Vivado Tool Research Articles

VLSI implementation of a modified min-max median filter using an area and power competent tritonic sorter for image denoising

The prominence of image processing in today’s cutting-edge technology is undeniable. Integrating software with hardware leverages both strengths, resulting in a real-time processing system that is efficient and streamlined. Raw images are usually affected by noise, which hinders the acquisition of good-quality and detailed images; hence, denoising becomes necessary. This paper proposes a modified min-max median (MMM) filter to remove impulse noise and a Tritonic sorter to localize corrupted pixels. The proposed denoising method focuses on localizing noisy pixels, unlike traditional denoising approaches, which focus only on noise detection and filtering. A min-max sheet provides the location of the corrupted pixels, and filtering is performed on them. The Tritonic Sorter, consisting of a max locator and a min locator, compares three input values and finds the minimum, maximum and median values among them. Compared to other state-of-the-art methods, the proposed method minimizes the number of comparators needed to carry out the sorting process. The proposed method was synthesized in the ZedBoard Zynq kit using the Vivado tool. The results show that the area improved by 27%, and the power improved by 16.23% compared with those of the existing method.

Design and implementation of low power multiplierless FIR filters on FPGA and ASIC

ABSTRACT This paper presents a low-power design and implementation approach for multiplierless FIR filters by reducing switching activity between filter coefficients using different optimisation algorithms. The objective function simultaneously minimises hamming distance between the consecutive filter coefficients, passband, and stopband ripples. Low-pass, high-pass, band-pass, and band-stop FIR filters of different order and word lengths are designed using improved grey-wolf optimisation. Comparison with grey-wolf optimisation, hybrid particle swarm optimisation, and grey-wolf optimisation, and whale optimisation algorithms is performed for different statistical parameters. The proposed filter is also compared with existing filter designs and shows considerable improvement in design metrics. For low-power implementation of designed FIR filters, carry-save-adder trees are utilised. FPGA and ASIC platforms are used for implementation. Basys-3 (Artix-7) FPGA board is targeted using the Vivado tool for FPGA implementation. Hardware design metrics such as slice LUTs, slice registers, slices, and dynamic power consumption are obtained. ASIC implementation is also performed using the Cadence Genus tool for a 45 nm Nan gate open cell library and total area, power, and delay are reported. The obtained results for FPGA slice utilisation and power consumption provide an average reduction of 61.39% and 74.13%, respectively. ASIC implementation provides an average 58.60% reduction in area-power product.

(Digital Presentation) Optimized Security: Enhancing the Modified Advanced Encryption Standard for Efficient Iot Application

The Modified Advanced Encryption Standard (MAES) emerges as a robust solution tailored for the unique challenges posed by Internet of Things (IoT) applications. In this paradigm, where resource constraints and energy efficiency are paramount, MAES optimizes the Advanced Encryption Standard (AES) to meet the specific demands of IoT devices. This modification involves a judicious trade-off between security and computational complexity, ensuring a delicate balance suitable for the constrained nature of IoT environments. MAES not only maintains the formidable security features of AES but also introduces tailored enhancements that cater to the low-power, low-memory, and high-throughput requirements of IoT devices. This abstract highlight the crucial role MAES plays in fortifying the security landscape of IoT, making it a compelling choice for safeguarding sensitive data in the era of interconnected and resource-limited devices.The test case bits will be used to pick the module. The key and input will then be chosen in accordance with the test case bit selection, and the module will generate the corresponding output and lower the clock cycles to 16 with 149.721W power dissipation. Verilog code was used to generate the MAES algorithm, which was intended for FPGA. Vivado tool is utilized for Synthesis and Simulation. The KINTEX-7 FPGA has successfully tested the design.

Novel Integer Division for Embedded Systems: Generic Algorithm Optimal for Large Divisors

The integer Constant Division (ICD) is the type of integer division in which the divisor is known in advance, enabling pre-computing operations to be included. Therefore, it can be more efficient regarding computing resources and time. However, most ICD techniques are restricted by a few values or narrow boundaries for the divisor. On the other hand, the main approaches of the division algorithms, where the divisor is variable, are digit-by-digit and convergence methods. The first techniques are simple and have less sophisticated conversion logic for the quotient but also have the problem of taking significantly long latency. On the contrary, the convergence techniques rely on multiplication rather than subtraction. They estimate the quotient of division providing the quotient with minimal latency at the expense of precision. This article suggests a precise, generic, and novel integer division algorithm based on sequential recursion with fewer iterations. The suggested methodology relies on extracting the division results for non-powers-of-two divisors from those for the closest power-of-two divisors, which are obtained simply using the right bit shifting. To the authors’ best knowledge of the state-of-the-art, the number of iterations in the recurrent variable division is half the divisor bit size, and the Sweeney, Robertson, and Tocher (SRT) division, which is named after its developers, involves <i>log</i><sub>2</sub>(n) iterations. The suggested algorithm has an [(m/(n-1))-1] number of recursive iterations, where m and n are the number of bits of the dividend and the divisor, respectively. The design is simulated in the Vivado tool for validation and implemented with a Zynq UltraScale FPGA. The technique performance depends on the number of nested divisions and the size of a LUT. The two factors change according to the value of the divisor. Nevertheless, the size of the LUT is proportional to the range and the number of bits of the divisor. Furthermore, the equation that controls the number of nested blocks is illustrated in the manuscript. The proposed technique applies to both constant and variable divisors with a compact hardware area in the case of constant division. The hardware implementation of constant division has unlimited values for dividends and divisors with a compact hardware area in the case of large divisors. However, using the design in the hardware implementation of variable division is up to 64-bit dividend and 12-bit divisor. The result analysis demonstrates that this algorithm is more efficient for constant division for large numbers.

High attenuation electromagnetic interface filter for effective processing of audio signals

Suppressing the noise or unwanted signal from the raw signal makes the system work efficiently. Electromagnetic interface (EMI) can cause the system/device to lose the data, damage the electronic equipment, interrupt the audio, or video signals, lead to poor reception, etc EMI filters are used in telecommunications, military equipment, satellite communication, etc At the industry level, EMI filters are used for home appliances, medical equipment, motor controls, test equipment, etc In this paper, active and passive EMI filters are designed to avoid or attenuate EMI or noise (unwanted EMI signal) and implemented on Xilinx Nexys 4 Artix 7 FPGA board. The filters provide a significant improvement in the attenuation of the EMI. MATLAB tool is used to design the filters, which are highly immune to undesired signals, give better stability, and perform over a wide range of frequencies. Depending on the filters’ coefficients, the frequency response will be changed. Phase response and amplitude response of the EMI filters are calculated. Insertion loss of the active filter is 1.5836, and for the passive filter, 1.9382. The gain of active and passive filters is 0.7359 and 0.912 respectively. The return loss of the active and passive EMI filters is 20 dB. HDL code is generated using MATLAB for the implementation of filter on FPGA. Using MATLAB HDL coder for implementing is new and it simplifies the design, as a result development time is reduced. Xilinx Vivado tool is used for the implementation of active filter. The total on-chip power is 0.146 W. Dynamic power is 0.049 W, and device static power is 0.097 W. The utilization of LUTs and slice registers are less, compared to the previous filter implementation, which leads to reduce the cost of hardware implementation.

FPGA Implementation of Power-efficient Multipliers for Digital Signal Processing Applications

Background:: Higher power consumption raises chip temperature because it draws more current from the power source, which directly affects how long the batteries survive in portable devices. High temperature affects the dependability and functionality of a circuit, requiring more complex packaging and cooling strategies. One of the most significant challenges in VLSI design is power consumption. The power consumption of the circuit rises with both transistor density and chip complexity. In addition, one of the essential building blocks of hardware in the majority of VLSI applications and digital signal processing systems is the multiplier. Aims and objective:: This study aimed to design and compare array multiplier, Vedic multiplier, and Wallace tree multiplier using variable bit lengths. Methodology:: In this paper, authors designed array multiplier, Vedic multiplier, and Wallace tree multiplier using variable bit lengths. For comparison, the VIVADO tool was used to simulate and synthesize multiplier outputs. Results:: Wallace tree multipliers resulted in 31.153mW, 13.220mW, 4.099mW, and 0.988 mW of power dissipation for 16-bit, 8-bit, 4-bit, and 2-bit, respectively. The best multiplier was designed using different logic like AOI, OAI, NAND-NAND, and NOR-NOR and was compared based on power dissipation. It was observed that 2.256mW power dissipation was observed for NOR-NOR logic, which was minimal among other logics. Conclusion:: The 4-bit Wallace multiplier using NOR-NOR logic was used for FPGA implementation, which can be used in digital signal processing applications.

High-Throughput MPSoC Implementation of Sparse Bayesian Learning Algorithm

In the field of sparse signal reconstruction, sparse Bayesian learning (SBL) has excellent performance, which is accompanied by extremely high computational complexity. This paper presents an efficient SBL hardware and software (HW&SW) co-implementation method using the ZYNQ series MPSoC (multiprocessor system-on-chip). Firstly, considering the inherent challenges in parallelizing iterative algorithms like SBL, we propose an architecture based on the iterative calculations implemented on the PL side (FPGA) and the iteration control and input management handled by the PS side (ARM). By adopting this structure, we can take advantage of task-level pipelines on the FPGA side, effectively utilizing time and space resources. Secondly, we utilize LDL decomposition to perform the inversion of the Hermitian matrix, which not only exhibits the lowest computational complexity and requires fewer computational resources but also achieves a higher level in the parallel pipeline mechanism compared with other alternative methods. Furthermore, the algorithm conducts iterations sequentially, utilizing the parameters derived from the previous dataset as prior information for initializing the subsequent dataset’s initial values. This approach helps to reduce the number of iterations required. Finally, with the help of Vitis HLS 2022.2 and Vivado tools, we successfully accomplished the development of a hardware design language and its implementation on the ZYNQ UltraScale+ MPSoC ZCU102 platform. Meanwhile, we have solved a direction of arrival (DOA) estimation problem using horizontal line arrays to verify the practical feasibility of the method.

Design and implementation of low power FPGA-based optimal multiband filter with Spline function for denoising ECG signals

This article presents the design and implementation of a low power FPGA-based optimal multiband filter with Spline function for denoising ECG signals. The proposed multiband filter design utilizes least mean square algorithm to determine the optimal filter coefficients for multiple frequency bands, while the Spline function is used to interpolate the filter coefficients within each band to achieve a smooth transition between adjacent bands. The experimental work is carried out with ECGID database and it shows that the proposed filter outperforms in terms of benchmark performance matrices SNR, MSE, CC and PRD. The filter is implemented on a low power FPGA platform, which allows for real-time processing of ECG signals with low power consumption. The experimental results are analyzed and compared for different architecture using the MATLAB and XILINX VIVADO tools. The serial architecture of proposed filter design is implemented on Artix 7 (XC7A35T) EDGE Board, utilizing 1932 LUT, 5299 FF, 1 DSP block and 0.158 W on-chip power. The experimental results indicate that the proposed filter design approach is efficient, effective, and suitable for implementation in compact biomedical devices.

Implementation of Fuzzy Logic Controller Algorithms with MF optimization on FPGA

In this work, we propose the design and implementation of a parallel-structured fuzzy logic controller with integral action and anti-windup. The Grey Wolf Optimization (GWO) optimization technique is used to optimize fuzzy rules, which allows for the complicated algebraic ideas of type 1 fuzzy logic algorithms to be reduced to straightforward numerical equations for FPGA target implementation. The techniques for operating a geared DC motor are optimized by the membership function structure of our controller's data propagation. Our proposed controller was implemented in Xilinx System Generator (XSG) and co-simulated on hardware and software with VIVADO and XSG tools.

Accelerating DSP Applications on a 16-Bit Processor: Block RAM Integration and Distributed Arithmetic Approach

Modern processors have improved performance but still face challenges such as power consumption, storage limitations, and the need for faster processing. The 16-bit Digital Signal Processors (DSPs) accelerate DSP applications by significantly enhancing speed and performance for tasks including audio processing, telecommunications, image and video processing, wireless communication, and consumer electronics. This paper presents a novel technique for accelerating DSP applications on a 16-bit processor by combining two methods: Block Random Access Memory (BRAM) and Distributed Arithmetic (DA). Integrating BRAM as a replacement for conventional RAM minimizes timing and critical route delays, improving processor efficiency and performance. Furthermore, the Distributed Arithmetic approach enhances performance and efficiency by utilizing precomputed lookup tables to expedite multiplication operations within the Arithmetic and Logic Unit (ALU). We use the Xilinx Vivado tool, a robust development environment for FPGA-based systems, for the design process and execute the hardware implementation using the Genesys2 Kintex board. The proposed work produces improved efficiency with a cycle per instruction of 2, where the delay is 2.009 ns, the critical path delay is 8.182 ns, and the power consumption is 4 mW.

Design and Implementation of High Speed 32-bit MAC Unit

Due to the recent advances in VLSI technology, the need for efficient real time signal processing units have increased. The multiplier-and-accumulator (MAC) unit is the essential element of the digital signal processor. The aim is to design an 32-bit MAC unit that can perform multiplication and accumulation operation. Hence designing an effective MAC unit with reduced latency is necessary for better performance. The proposed MAC unit uses Carry-Select adder and Vedic multiplier which offers better speed (1.746 ns) in comparison with MAC unit designed using Ripple carry adder (1.782 ns). Urdhva tiryaghbyam sutra is the base sutra used in Vedic multiplier. The design was implemented in Verilog HDL using Xilinx Vivado tool and synthesis was done using Cadence Genus tool.

FPGA Implementation of a Novel Multifunction Modulo (2n ± 1) Multiplier Using Radix-4 Booth Encoding Scheme

The residue number system is widely used in applications such as communication systems, cryptography, digital filters, digital signal processors, fault-tolerant detection, and so on. This paper proposes a multifunction modulo (2n ± 1) multiplier based on the radix-4 Booth encoding scheme that can operate both modulo (2n − 1) and modulo (2n + 1) multipliers using the same hardware structure with only one control signal. A novel modulo (2n ± 1) multiplier based on radix-4 Booth encoding is proposed that can achieve superior performance, with low power, fast operation, high area efficiency, and low area-delay product (ADP) and power-delay product (PDP) compared with similar modified Booth-encoding methods. In addition, by integrating the separate modulo functions of the modulo (2n − 1) multiplier and modulo (2n + 1) multiplier into a single multifunction modulo (2n ± 1) multiplier, the proposed method can save up to 52.59% (n = 16) of hardware area, up to 5.45% (n = 32) of delay time, up to 49.05% (n = 16) of dynamic power, up to 50.92% (n = 32) of ADP, and up to 50.02% (n = 32) of PDP compared with the original separate circuits merged together. Furthermore, the operation ranges of the multiplicand and multiplier of the proposed modulo (2n + 1) multiplier and modulo (2n − 1) multiplier are {0, 2n + 1} and {0, 2n}, respectively, which are wider than for other reported hardware structures. The hardware area, power consumption, and delay time are simulated and verified using Verilog HDL and Xilinx FPGA (Field Programmable Gate Array) Vivado tools. The Xilinx Artix-7 XC7A35T-CSG324-1 FPGA chipset is adopted in the proposed work.

Secure double MAC implementation for STBC based FECG monitoring

One of the best methods for assessing a baby’s health is foetal electrocardiography (FECG). Previously restricted to more widespread global disorders such as common ischemia, it is new way to investigating foetal heart rate irregularities. Current prenatal monitoring practices ignore critical FECG waveform elements that are the foundation of both pediatric, adult cardiac assessment, and instead of focusing solely on the foetal heart rate. In this paper we proposed Double Multiply-and-Accumulate (MAC) approach used for package operators into a single DSP block of commercial FPGAs, theoretically doubling the calculation speed for FECG monitoring. For a variety of technical reasons, they were using the Space-Time Block Code (STBC) monitoring mode of operation. To strengthen the security of FECG monitoring, the Advanced Encryption Standard (AES) method may be used with the double MAC operators using STBC based FECG monitoring that has been developed. The solution was then assessed using state-of-the-art the Space-Time Block Code (STBC) based FECG techniques, and its validity was confirmed using Verilog simulation and FPGA synthesis. The calculation throughput of an STBC-based FECG monitoring system was found to be doubled using the Double MAC approach. Our implementation result demonstrates that keys are necessary for 128-bit AES encoding and decoding operations via VHDL-coded transformations. It is now more vital than ever to do a feasibility analysis of any hardware design due to the increase in the number of ways presented for minimizing noise. The efficiency increased (92%), and the delay was decreased to 19.35 ns by employing this double MAC architecture. The simulation results demonstrate that transformations for coding on an FPGA are implemented using the Xilinx VIVADO tool.

FPGA-based fault analysis for 7-level switched ladder multi-level inverter using decision tree algorithm

The proposed method involves the fault analysis of the inverter switches present in the multi-level inverter (MLI) circuitry. The decision tree machine learning algorithm is incorporated for the fault analysis of the inverter switches. The multi-level inverter utilized in this work is a 7-level switched ladder multi-level inverter. There is 4 number of switches in the design of a 7-level inverter driven by the non-carrier digital pulse width modulation signals. The non-carried-based digital pulse-width modulator (DPWM) generation is generated using the event angle for the 7-level of the switched ladder inverter. The proposed method investigates the stuck-at-fault occurrences of the 4 switches in the inverter by manipulating the decision tree parameters such as entropy, information gain, and decision tree. Based on the decision tree, the very high-speed integrated circuit hardware description language (VHDL) code is developed by making use of the behavioral modeling and validated for the power, area in the Xilinx Vivado tool. The real-time feasibility is verified for the proposed method by synthesizing the developed VHDL code in the field programmable gate array (FPGA) device.

A new 4‐D hyperchaotic two‐scroll system with hidden attractor and its field‐programmable gate array implementation

SummaryThis research work reports the finding of a new 4‐D hyperchaotic two‐scroll system having three second‐order nonlinear terms. It is detailed that the system does not have any rest point for non‐zero values of the system parameters. Thus, we deduce that the new hyperchaotic system has a hidden attractor. The main findings of the new hyperchaotic system include a detailed bifurcation analysis, coexisting attractors, and offset‐boosting control. The new 4‐D hyperchaotic two‐scroll system with hidden attractor is prototyped using the field‐programmable gate array (FPGA) Zybo Z7‐20 development board, Xilinx Vivado tool, and the hardware description by VHDL. It is highlighted that the simulation of the circuit design, and the experimental results from the FPGA synthesis, all of them are in good agreement with theoretical simulations.

Heterogenous ensemble learning driven multi-parametric assessment model for hardware Trojan detection

Semiconductor technologies have gained wide-spread attention across industries due to its use in varied digital signal processing units, healthcare-devices, industrial communication, science and technologies, entertainment, smart devices etc. However, high design-complexities, untrusted foundries, third-party processors etc., have raised the concern of intrusion, particularly Hardware Trojans. Hardware Trojan, a specifically designed micro-intruder that can cause data breaches, system malfunctions etc. And hence may result disastrous consequences. To alleviate such problems, though different methods have been suggested for Trojan detection; however, pre-manufacturing methods can't guarantee Trojan-free design due to non-trusted Foundries and Third-party IPs. Similarly, post-manufacturing methods like side channel analysis or gate -level netlist are limited due to highly complex design, large structure and unavailability of universal golden design structures. Considering it as motivation, this paper proposes a robust register transfer logic (RTL) analysis assisted multi-parameter-based machine learning-driven Hardware Trojan detection system. We applied delay, power consumption and resource utilization profiles to perform Trojan detection over AES-256 circuits. Aforesaid features were extracted using VIVADO tool, which were further employed for resampling process using SMOTE, SMOTE-ENN, SMOTE-Borderline algorithms. Here, the use of resampling intended to alleviate data-imbalance or skewness. Moreover, it helped retaining sufficiently large features for machine learning based training. The resampled features were processed for feature selection using Significant Predictor Test, Cross-Correlation Test and Principal Component Analysis (PCA), distinctly. The selected features were trained using a novel heterogenous ensemble learning model encompassing a total of 11 base-classifiers belonging to Naïve Bayes, Neuro-computing, Decision Tree, Random Forest, Extra Tree classifier and Bagging-AdaBoost algorithms. Applying the maximum voting ensemble, the proposed model performed path-level Trojan detection, where the simulated results affirmed accuracy, F-Measure and Area Under Curve (AUC) of almost 100%, which is higher than any known approaches towards Hardware Trojan detection.

Design of RISC Processor with IEEE754 Standard Floating-Point Instruction Set in FPGA using VHDL for Digital Signal Processing Applications

The design of RISC processors, which are the key of digital signal processing applications, are increasing in reconfigurable hardware. FPGAs are suitable reconfigurable hardware for RISC processor design, with advantages such as parallel processing and low power consumption. In this study, the design of the 32-bit RISC processor in a FPGA is presented. The designed RISC processor contains IEEE754 standard floating-point number processing unit, which is executed in a one clock cycle. The verification of the processor is performed for the Zynq-7000 SoC Artix-7 FPGA chip in the Xilinx Vivado tool. Classification of an artificial neural network using the iris dataset is carried out in this designed RISC processor. In order to compare the performance, the same artificial neural network is executed in real time within the dual-core ARM Cortex-A9 processor in the operating system of the Zynq-7000 SoC. The results show that the RISC processor designed in the FPGA executes at 20x less clock cycles and 3x higher speed compared to the ARM processor.

GPS Receivers Spoofing Detection Based on Subtractive, FCM and DBSCAN Clustering Algorithms

GPS receivers have a wide range of applications, but are not always secure. A spoofing attack is one source of conscious errors in which the counterfeit signal overcomes the authentic GPS signal and takes control of the receiver’s operation. Recently, GPS spoofing attack detection based on computational algorithms, such as machine learning, classification, wavelet transform and clustering, has been developing. This paper proposes multiple clustering algorithms for accurately clustering the authentic and spoofing signals, called subtractive, FCM and DBSCAN clustering. The spoofing attack is recognized using two distinct features: moving phase detector variance and norms of correlators. Spoofing and authentic signals have different patterns in the proposed features. According to the Dunn and Silhouette indexes, the validation of the results is investigated. The Dunn values for the proposed approaches are 0.8592, 0.5285 and 0.6039 for DBSCAN, FCM and subtractive clustering, respectively. Also, the DBSCAN algorithm is implemented at the RTL level because of its highest value for the Dunn index and algorithm verifiability. Using the Vivado tools, this algorithm is implemented and designed on a Xilinx Virtex 7 xc7vx690tffg1930-3 hardware device for two-dimensional data with 32-bit accuracy and 130 data points.

FPGA implementation of AAD pooling unit and performance analysis

Convolutional Neural Network (CNN) has been witnessing a massive growth for its various applications in different fields. It is a category of Neural Network or Deep learning that is being used in text detection, image classification, etc. It is also very effective for the classifications which are non-image like audio classifications, signal data classifications, etc. CNN is composed of convolutional layer, pooling layer and finally the fully connected layer. In this work, we mainly focus on pooling layer which impacts accuracy and speed of CNN. This work implements validation of CNN based CIFAR-10 classifier and Field Programmable Gate Array (FPGA) implementation of Absolute Average Deviation (AAD) Pooling unit. Pooling techniques like max pooling, average pooling, mixed pooling, min pooling, etc., are currently being used. This work uses AAD pooling in CNN to support that this pooling is having higher accuracy, i.e., 89% and less computational complexity. A benchmark CNN structure using TensorFlow is adopted to quantify the performance of the AAD pooling unit. Further, Register Transfer Level (RTL) coding is done in Verilog HDL and the testbench is developed. The FPGA implementation is carried out using the Xilinx Vivado tool.

A Comprehensive Survey on Lightweight Asymmetric Key Cryptographic Algorithm for Resource Constrained Devices

Elliptic Curve Cryptography, being a popular lightweight asymmetric key cryptographic algorithm that is widely adapted to meet high security requirement of resource constrained devices, were surveyed in this work. Further, ECC-based ElGamal cryptosystem, Elliptic Curve Digital Signature Algorithm, and Elliptic Curve Diffie Hellman Key Exchange Algorithm have been comprehensively reviewed with its characteristics and preferred applications. In addition, few related work are analyzed and suggestions for suitable target applications were provided. Moreover, ECC being a popular asymmetric key cryptographic technique is reported to be modeled using Vivado tool for various target implementation on FPGA devices. Techniques that enhances throughput, area, and computation time that caters for IoT applications were also reviewed. Design implementations on the advanced FPGA boards for IoT device/similar applications were also analyzed and compared.