FPGA implementation of AAD pooling unit and performance analysis

Abstract

Convolutional Neural Network (CNN) has been witnessing a massive growth for its various applications in different fields. It is a category of Neural Network or Deep learning that is being used in text detection, image classification, etc. It is also very effective for the classifications which are non-image like audio classifications, signal data classifications, etc. CNN is composed of convolutional layer, pooling layer and finally the fully connected layer. In this work, we mainly focus on pooling layer which impacts accuracy and speed of CNN. This work implements validation of CNN based CIFAR-10 classifier and Field Programmable Gate Array (FPGA) implementation of Absolute Average Deviation (AAD) Pooling unit. Pooling techniques like max pooling, average pooling, mixed pooling, min pooling, etc., are currently being used. This work uses AAD pooling in CNN to support that this pooling is having higher accuracy, i.e., 89% and less computational complexity. A benchmark CNN structure using TensorFlow is adopted to quantify the performance of the AAD pooling unit. Further, Register Transfer Level (RTL) coding is done in Verilog HDL and the testbench is developed. The FPGA implementation is carried out using the Xilinx Vivado tool.