Viterbi Decoder Research Articles

Implementation of Efficient Stopping Criteria for Turbo Decoding

The cellular systems with 4th generation, Long Term Evolution (LTE) standard have been transmitted the data at higher rates than the 3G, and 2G systems, in an ever-crowded frequency spectrum. This transmission needs more accuracy, high reliability, and throughput with a low area and power consumption. Therefore, it requires an efficient error control coding. Turbo code is used for LTE system for its good error correction ability at low signal to noise power ratio which can approach Shannon limit performance for large frame lengths. This paper presents a simple and efficient modification that can be applied to all present stopping criterion (SC) to achieve the quality of service mentioned previously. It’s proved that using a trimmed sequence of log-likelihood values (LLR) instead of the full length in the algorithms of stopping the iterative decoding has a significant impact on the utilized silicon area and throughput without a significant sacrifice in performance. It also presents a comparison of designing the Soft-Output Viterbi (SOVA) decoder using different arbitrary-precision fixed data types that offers by Vivado high-level synthesis (HLS) instead of the costlier float representation to reduce processing time and consumed area. Due to its high flexibility in designing and implementing prototype systems, the FPGA device (Kintex-7, Xilinx part number XC7K325T-2FFG900C) was utilized with different parallelism and loop pipelining directives to ensure acquiring the targeted initiation interval and silicon area.

Wave Pipelined VLSI Architecture for a Viterbi Decoder Using Self Reset Logic with 0.65nm Technology

In 3G mobile terminals the Viterbi Decoder consumes approximately one third of the power consumption of a base band mobile transceiver. Viterbi decoders employed in digital wireless communications are complex and dissipate large power. A low power Viterbi decoder is designed in circuit level using self reset logic and wave pipelining technique is implemented for high speed operation. The Viterbi decoder consists of four units like branch metric unit, add compare and select unit and the survivor path memory unit. All these units are designed using the self reset logic and wave pipelining, and simulated with its layout using MICROWIND TOOL in the 0.65nm technology, 1.8V Vdd and at a frequency of 10GHz. The simulation result shows that the power consumption is reduced by 70.55% and the speed of the circuit is increased by 45.83% compared to the Single Rail Domino Logic for constraint length of K =3 to 7.

Collision Resolution With FM0 Signal Separation for Short-Range Random Multi-Access Wireless Network

In internet of things, a central node to multiple sensor nodes is usually a short-range communication network, which generally uses random multiple access to resolve collision at a media access control (MAC) layer. In this case, the communication efficiency is not optimal. On the other hand, its efficiency can be improved in separated collision resolution, where collision signals can be separated and then decoded. For the resolution, good coding techniques can improve the performance of collision resolution. However, the conventional coding techniques usually need the signal fading coefficient estimated or be known in advance. The condition is not always satisfied in the short-range network. This paper proposes a finite-symbol separation Viterbi decoder (FSVD) which does not need to know the fading coefficient. Through the estimation of a dictionary matrix, the uncertainty of signal separation can be eliminated, and thus obtain more accurate likelihood distances and improve the decoding accuracy. In experiments, we establish two ultra-high frequency (UHF) short-range wireless networks based on an FM0 code, using a simulation and a software radio platform, respectively. The experimental results show that the throughput of FSVD reaches about 0.61, which is about 0.25 higher than that of a traditional ALOHA network.

Skew Convolutional Codes.

A new class of convolutional codes, called skew convolutional codes, that extends the class of classical fixed convolutional codes, is proposed. Skew convolutional codes can be represented as periodic time-varying convolutional codes but have a description as compact as fixed convolutional codes. Designs of generator and parity check matrices, encoders, and code trellises for skew convolutional codes and their duals are shown. For memoryless channels, one can apply Viterbi or BCJR decoding algorithms, or a dualized BCJR algorithm, to decode skew convolutional codes.

Optimization algorithms for improving the performance of permutation trellis codes

In this paper, soft-decision (SD) decoders of permutation trellis code (PTC) with M-ary frequency shift keying are designed using three optimization algorithms and presented in four decoding schemes. In a concatenated code such as PTC, the Viterbi decoder for the outer convolutional code provides maximum likelihood decoding. Hence, the error correction performance is dependent on the decoding scheme used for the inner code. Due to the structure of the encoder with the modulation scheme, the channel output can be interpreted as an assignment problem. SD decoding can then be designed accordingly, using the presented, low-complexity optimization-based schemes. The bit error rate (BER) performance of the schemes are simulated in an additive white Gaussian noise (AWGN) and powerline communication (PLC) channel. The complexities of the schemes are also presented. The performance of the SD schemes are compared with the existing SD threshold detector, with BER results showing significant coding gain for certain codebooks. From the results, a reasonable trade-off between the complexity and coding gain is observed for a noisy channel such as the PLC channel.

ANN-Assisted Real-Time Blind Signal Detection Over Time-Varying Doubly-Stochastic Poisson Channel for Indoor Optical Wireless Communications

In this letter, we present a new real-time blind signal detection technique for indoor optical communications using a supervised learning framework in an artificial neural network (ANN). We model the optical channel as a time-varying doubly-stochastic Poisson process. To compare the performance of the proposed ANN network, we present an iterative method for joint channel estimation and symbol detection using expectation-maximization (EM) and Viterbi decoding and demonstrate that the bit error rate (BER) performance of the proposed technique is better than that of the Viterbi decoding. The proposed scheme is found to be resilient to indoor channel dynamics and can achieve a good BER performance over a wide range of channel variations.

Low power sleepy keeper technique based VLSI architecture of Viterbi decoder in WLANs

ABSTRACT .Wireless communication technologies have advanced from cellular networks to satellite systems which create an advancing demand for low power battery operated decoding unit. Widely used error correction technique in the wireless communication systems is the channel coding. In channel coding, convolutional codes are commonly used for the transmission of data over a noisy channel. The methodologies adopted in the proposed design to achieve low power and increase in performance is by designing the architecture of the Viterbi decoder at circuit level design using a sleepy keeper technique, which curtails the leakage power dissipation. The second method is by including the modified register exchange algorithm, which reduces the occurrence of error probability with low power in signal transmission in the wireless domain. Simulation of the design is executed in 45nm TSMC in Tanner-SPICE. Promising results are obtained with reduction in power 31.54% with the CMOS technology for the WLAN frequency of 2.5MHz. BER performance of the design also found to be low in the channel environment.

Viterbi Decoder to Resolve Angular Ambiguity in Digital Beamforming With Widely Spaced Radar Front Ends

This article introduces a precise radar-based direction-of-arrival measurement system using a Viterbi decoder. Based on the frequency-modulated continuous-wave principle, the presented method employs both the frequency difference and the round-trip phase difference of the radio wave signal impinging at two widely spaced receiving antennas, thereby accomplishing highly accurate and absolute measurements of the direction-of-arrival. In order to resolve angular ambiguity, which is inherently caused by the $2 \pi $ ambiguity in phase measurement, the proposed Viterbi decoder determines the most likely sequence of direction-of-arrivals of the impinging radio wave signals. For proof of concept, experiments based on a 77 GHz radar unit equipped with one transmitting and two widely spaced receiving antennas were carried out. The measurement results show that angular ambiguity can be resolved by the presented Viterbi decoder since absolute, accurate, and repeatable direction-of-arrival estimates were obtained, even for receiver antenna spacings significantly larger than the signal wavelength.

Radar Distance Measurement With Viterbi Algorithm to Resolve Phase Ambiguity

In this article, a precise phase-based radar distance measurement system using a Viterbi decoder to resolve phase ambiguity is presented. Relying on the frequency-modulated continuous-wave radar principle, the introduced method evaluates both the frequency and the phase of the intermediate frequency signal, thus achieving absolute distance measurement with high accuracy. To avoid ambiguity in the distance estimates by half the wavelength of the radio frequency signal, which commonly arises due to 2π ambiguity in the measurement of the phase, the proposed Viterbi-based method estimates the most likely sequence of distances between the radar front end and the target. To verify the system concept, measurements using a commercial 77 GHz radar module were carried out, whereby the contour of a predefined surface containing steps in the height profile had to be determined. The experimental results confirm that the Viterbi-based approach is suitable to resolve phase ambiguity since accurate and repeatable distance estimates were obtained.

Efficient Open Source Software Radio on Heterogeneous Multicore Embedded Platforms

Software radio is a common technique in modern communications equipment, and it is frequently implemented using heterogeneous multicore processors because of its high computational requirements. Programming such systems is still a challenging task and developers rely often on standard parallel APIs and frameworks such as OpenMP and OpenCL. These tools, however, present some limitations when more than one algorithm has to be accelerated. The typical workload of a software radio usually includes several compute-intensive algorithms so it might be still better served by more specific tools, especially on embedded platforms. In this article, a development methodology for implementing software radio applications in heterogeneous multicore embedded platforms is proposed. The methodology is based on GNU radio, a free and open source software toolkit. To validate the methodology, a DVB–T receiver has been ported to an embedded heterogeneous multicore platform as a proof-of-concept. The results show that two different compute-intensive algorithms, Viterbi decoder, and FFT, can be simultaneously accelerated, improving the DVB–T receiver performance by 63%.

Regenerativity of Viterbi Process for Pairwise Markov Models

For hidden Markov models one of the most popular estimates of the hidden chain is the Viterbi path -- the path maximising the posterior probability. We consider a more general setting, called the pairwise Markov model (PMM), where the joint process consisting of finite-state hidden process and observation process is assumed to be a Markov chain. It has been recently proven that under some conditions the Viterbi path of the PMM can almost surely be extended to infinity, thereby defining the infinite Viterbi decoding of the observation sequence, called the Viterbi process. This was done by constructing a block of observations, called a barrier, which ensures that the Viterbi path goes trough a given state whenever this block occurs in the observation sequence. In this paper we prove that the joint process consisting of Viterbi process and PMM is regenerative. The proof involves a delicate construction of regeneration times which coincide with the occurrences of barriers. As one possible application of our theory, some results on the asymptotics of the Viterbi training algorithm are derived.

Using Punctured Convolution Coding (PCC) for Error Correction in Chipless RFID Tag Measurement

This letter presents an error correction technique for chipless radio frequency identification (RFID) tags using punctured convolution coding (PCC). We use a frequency signature-based chipless RFID tag which can encode Tag IDs at different resonance frequencies. Due to the presence of unwanted interference during communication, the backscatter tag response undergoes an abrupt change in amplitude and a shift in frequency, resulting in missing bits or errors. Normally, error correction in RFID technology requires intelligent behavior on the tag and in the reader. Our proposed measurement technique abandons the need for an integrated circuit (IC) and memory on the tag. Alternatively, the error correction functionality is executed during the design and fabrication process in chipless RFID tags. The PCC-based chipless RFID tag is then detected by the detection technique based on the presence of tag resonance resembling logic “1” and “0,” which is then decoded using Viterbi decoder to obtain the original source data. The proposed technique can detect error and recover missing bits in the chipless RFID system.

Online Speech Recognition Using Multichannel Parallel Acoustic Score Computation and Deep Neural Network (DNN)- Based Voice-Activity Detector

This paper aims to design an online, low-latency, and high-performance speech recognition system using a bidirectional long short-term memory (BLSTM) acoustic model. To achieve this, we adopt a server-client model and a context-sensitive-chunk-based approach. The speech recognition server manages a main thread and a decoder thread for each client and one worker thread. The main thread communicates with the connected client, extracts speech features, and buffers the features. The decoder thread performs speech recognition, including the proposed multichannel parallel acoustic score computation of a BLSTM acoustic model, the proposed deep neural network-based voice activity detector, and Viterbi decoding. The proposed acoustic score computation method estimates the acoustic scores of a context-sensitive-chunk BLSTM acoustic model for the batched speech features from concurrent clients, using the worker thread. The proposed deep neural network-based voice activity detector detects short pauses in the utterance to reduce response latency, while the user utters long sentences. From the experiments of Korean speech recognition, the number of concurrent clients is increased from 22 to 44 using the proposed acoustic score computation. When combined with the frame skipping method, the number is further increased up to 59 clients with a small accuracy degradation. Moreover, the average user-perceived latency is reduced from 11.71 s to 3.09–5.41 s by using the proposed deep neural network-based voice activity detector.

Comprehensive Analysis and Optimization of Reliable Viterbi Decoder Circuits Implemented in Modular VLSI Design Logic Styles

The Viterbi Algorithm is a recursive optimal solution for estimating the most likely state sequence of discrete-time finite-state Markov process and Hidden Markov Models (HMM) observed in memoryless noise. The Viterbi algorithm is extensively used for decoding convolutional codes, in the constraint length k that encompasses its use in digital communications specifically in satellite and cellular communications. Storage devices to speed up access, speech synthesis and recognition technologies use the Viterbi algorithm or its variants. In this paper low-power, high-speed and reduced transistor count Viterbi decoding circuits with enhanced error detection capabilities are designed and implemented with signature-based error detection schemes in three design logic styles primarily Conventional CMOS, Hybrid logic and GDI. The significance of the work is the upshot of realizing low latency and low power dissipation with high reliability in the iterative process of finding the least path metric by superseding the subtractor in CSA & PCSA circuits with an optimized comparator. When evaluated against the Traditional/Benchmark CSA & PCSA circuits, the Conventional CMOS design approach attains low power consumption and high accuracy with a reduction in average power dissipation by 4.69% and 3.83% and an improvement in delay performance by 7.89% and 3.79% respectively, with a tradeoff for high area utilization. Whereas, the GDI design approach results in an extreme reduction of transistor count by 71.52% and 74.94% with a weaker logic swing for CSA & PCSA units respectively, complimented by an increase in power dissipation (approximately multiplied by a factor of 5) and deterioration in delay performance by one order of magnitude. The Hybrid logic stages CSA & PCSA units that are 32.52% and 9.27% faster and achieve optimization in area utilization by 48.68% and 51.09% respectively, at the expense of elevated power dissipation by one order of magnitude. All the circuits were designed and simulated using GPDK 90 nm technology libraries on Cadence Design Suite 6.1.6 platform at 27 °C temperature on 1.2 V supply-rail and SPICE codes were generated as well.

Recurrent neural network based turbo decoding algorithms for different code rates

Application of deep learning to error control coding is gaining special attention and neural network architectures on decoding are approached to compare with conventional ones. Turbo codes conventionally use BCJR algorithm for decoding. In this paper, performances of neural Turbo decoder and deep learning-based Turbo decoder are examined. A category of sequential codes are utilized to construct the RSC (Recursive Systematic Convolutional) codes as basic elements for Turbo encoder. Sequential codes suit the requirement of memory element present in convolution codes, which act as components for Turbo encoder. Turbo decoders are constructed by two means; as neural Turbo decoder and deep learning Turbo decoder. Both structures are based on recurrent neural network (RNN) architectures. RNN architectures are preferred due to the presence of memory as a feature. BER performance of both is compared with that of a convolutional Viterbi decoder in awgn channel. Both the structures are studied for different input data-lengths and code rates.

A Viterbi decoder and its hardware Trojan models: an FPGA-based implementation study.

Integrated circuits may be vulnerable to hardware Trojan attacks during its design or fabrication phases. This article is a case study of the design of a Viterbi decoder and the effect of hardware Trojans on a coded communication system employing the Viterbi decoder. Design of a Viterbi decoder and possible hardware Trojan models for the same are proposed. An FPGA-based implementation of the decoder and the associated Trojan circuits have been discussed. The noise-added encoded input data stream is stored in the block RAM of the FPGA and the decoded data stream is monitored on the PC through an universal asynchronous receiver transmitter interface. The implementation results show that there is barely any change in the LUTs used (0.5%) and power dissipation (3%) due to the insertion of the proposed Trojan circuits, thus establishing the surreptitious nature of the Trojan. In spite of the fact that the Trojans cause negligible changes in the circuit parameters, there are significant changes in the bit error rate (BER) due to the presence of Trojans. In the absence of Trojans, BER drops down to zero for signal to noise rations (SNRs) higher than 6 dB, but with the presence of Trojans, BER doesn’t reduce to zero even at a very high SNRs. This is true even with the Trojan being activated only once during the entire duration of the transmission.

Joint Viterbi detection and decoding algorithm for bluetooth low energy systems

An efficient joint Viterbi detection and decoding (JVDD) algorithm for a bluetooth low energy (BLE) system is proposed. Since the convolutional coded Gaussian minimum-shift keying (GMSK) signal is specified in the BLE 5.0 standard, two Viterbi processors are needed for detection and decoding. However, the proposed JVDD scheme uses only one Viterbi processor by modifying the branch metric with inter-symbol interference information from GMSK modulation; therefore, the hardware complexity can be significantly reduced without performance degradation.

Computationally efficient 104 Gb/s PWL-Volterra equalized 2D-TCM-PAM8 in dispersion unmanaged DML-DD system.

Two-dimensional eight-level pulse amplitude modulation with trellis-coded modulation (2D-TCM-PAM8) is proposed to overcome the bandwidth limitation for high-speed signal transmission due to its high spectral efficiency. However, the high coding gain of the TCM can only be achieved in bandlimited additive white Gaussian noise (AWGN) channels and cannot be achieved in nonlinear channels without any equalizers. In the directly modulated laser and direct detection (DML-DD) transmission system, the transceiver nonlinearities and the interaction between DML chirp and fiber dispersion will introduce nonlinear distortion. To compensate for the nonlinear distortion, we propose a computationally efficient piecewise linear (PWL)-Volterra equalizer. In this equalizer, we first use the PWL to correct the skewed eye diagram and then employ a simple 2nd order Volterra to compensate for the residual nonlinear distortions. By using the PWL-Volterra equalizer prior to the Viterbi decoder, the high coding gain of TCM can be achieved. In the experiment, a 104 Gb/s 8-state 2D-TCM-PAM8 signal generated in a ∼ 20 GHz DML is successfully transmitted over 10 km standard single-mode fiber (SSMF) in C band, with the bit error ratio (BER) below the HD-FEC limit of 3.8 × 10-3. Compared to only using the conventional 2nd order Volterra equalizer with a similar BER performance, the PWL-Volterra equalizer shows 29% computational complexity reduction.

Low Complexity Viterbi Decoder for RSCC Concatenated Codes

One of the primary obstacles to achieving reliable communication transmission for aerospace applications is the power constraints. Therefore, it is appealing to use powerful channel coding techniques with small complexity of decoding. The robust forward error correction scheme using Reed-Solomon as outer code concatenated with convolutional as inner code is an appealing scheme whose apps are commonly used in wireless and space transmissions. In this work we aim to reduce the complexity of the convolutional code decoding process as the number of computations and memory need increases exponentially with the code’s constraint length. We use the Adaptive Viterbi Algorithm to bring Viterbi decoder with small complexity. The proposed work yields approximately the same error performance as the conventional concatenated Reed-Solomon convolutional, while requiring a substantially smaller average number of computations for the convolutional code decoding process.

Radiation tolerant viterbi decoders for on-board processing (OBP) in satellite communications

Modern satellite communication systems require on-board processing (OBP) for performance improvements, and SRAM-FPGAs are an attractive option for OBP implementation. However, SRAM-FPGAs are sensitive to radiation effects, among which single event upsets (SEUs) are important as they can lead to data corruption and system failure. This paper studies the fault tolerance capability of a SRAM-FPGA implemented Viterbi decoder to SEUs on the user memory. Analysis and fault injection experiments are conducted to verify that over 97% of the SEUs on user memory would not lead to output errors. To achieve a better reliability, selective protection schemes are then proposed to further improve the reliability of the decoder to SEUs on user memory with very small overhead. Although the results are obtained for a specific FPGA implementation, the developed reliability estimation model and the general conclusions still hold for other implementations.