Vision Chip Architecture Research Articles

A 1000 frames/s Vision Chip Using Scalable Pixel-Neighborhood-Level Parallel Processing

This paper presents a novel vision chip architecture based on pixel-neighborhood-level parallel processing. In the architecture, an 8-b RISC processing core is embedded in an $8\times 8$ array of digital pixel sensors on the same focal plane. These neighborhood processors (NPs) are tiled in a 2-D array to form the final imager resolution. Program execution is carried out in parallel across the array of pixel-neighborhood processing cores, allowing for direct scalability in terms of resolution, without reduction in processing speed or frame rate. To accomplish this, a compact, low-complexity NP architecture along with a general-purpose, 8-b instruction set has been designed and implemented. A prototype vision chip containing an $8 \times 10$ array of NPs with a $64 \times 80$ resolution has been designed and fabricated in a 0.13- $\mu \text{m}$ 1P8M CMOS fabrication process. The system is reprogrammable and can perform a wide range of image and video processing tasks. Several example algorithms are implemented and tested on the single-chip vision system to demonstrate the functionality of pixel-neighborhood-level parallelism, including 1000-frames/s object tracking.

Pixel‐parallel feature detection on vision chip

Pixel-parallel FAST and SIFT feature detection algorithms are proposed, which are suitable for the vision chip architecture. The proposed algorithms can execute the FAST and SIFT feature detections on the vision chip in a pixel-parallel manner. The Feature detection utilising the proposed algorithms can be realised by basic logic and arithmetic operations. Experiments and detailed analysis show that the proposed algorithms can perform feature detection on the vision chip at a higher speed compared with that on a general processor or an application-specific circuit.

A massively parallel keypoint detection and description (MP-KDD) algorithm for high-speed vision chip

This paper proposes a massively parallel keypoint detection and description (MP-KDD) algorithm for the vision chip with parallel array processors. The MP-KDD algorithm largely reduces the computational overhead by removing all floating-point and multiplication operations while preserving the currently popular SIFT and SURF algorithm essence. The MP-KDD algorithm can be directly and effectively mapped onto the pixel-parallel and row-parallel array processors of the vision chip. The vision chip architecture is also enhanced to realize direct memory access (DMA) and random access to array processors so that the MP-KDD algorithm can be executed more effectively. An FPGA-based vision chip prototype is implemented to test and evaluate our MP-KDD algorithm. Its image processing speed reaches 600-760 fps with high accuracy for complex vision applications, such as scene recognition.

Heterogeneous vision chip and LBP‐based algorithm for high‐speed tracking

A local binary pattern (LBP)-based tracking algorithm and a novel heterogeneous vision chip architecture that implements the algorithm in high speed are proposed. The algorithm is more robust than previously reported high-speed tracking algorithms. The proposed vision chip architecture adopts multiple levels of parallel processors to execute the algorithm in pixel-parallel and patch-parallel ways. Experimental results show that the proposed implementation can achieve 1000 fps robust tracking.

A SIMD Cellular Processor Array Vision Chip With Asynchronous Processing Capabilities

This paper describes an architecture and implementation of a digital vision chip that features mixed asynchronous/synchronous processing techniques. The vision chip is based on a massively parallel cellular array of processing elements, which incorporate a photo-sensor with an ADC and digital processing circuit, consisting of 64 bits of local memory, ALU, flag register and communication units. The architecture has two modes of operation: synchronous SIMD mode for low-level image processing based on local pixel data, and continuous-time mode for global operations. Additionally, the periphery circuits enable asynchronous address extraction, fixed pattern addressing and flexible, random access data I/O. A 19 × 22 proof-of-concept array has been manufactured in 0.35 μm CMOS technology. The chip delivers 15.6 GOPS for binary and 1 GOPS for grayscale operations dissipating 26.4 mW, while operating at 2.5 V and 75 MHz clock. Experimental measurements indicate that the presented concept favorably compares with other digital and analog vision chips. The results of low- and medium-level image processing on the chip are presented.

A vision chip with column-level amplification of optical data signals for indoor optical wireless local area networks

We present a vision chip architecture with column-level photo-amplification of optical data signals for optical wireless local area networks (LANs) to reduce the pixel area. Based on the architecture, we have fabricated a prototype vision chip in a standard 0.8 μm bipolar complementary metal-oxide-semiconductor (BiCMOS) technology. The device offers position detection of other optical transceivers in the LAN and 4-ch concurrent high-speed optical data acquisition. A data rate of 400 Mbps was demonstrated. The pixel size was 125 μm square, which can be shrunk to smaller than around 60 μm square in 0.35 μm or more advanced BiCMOS or CMOS technologies.

Column-Parallel Vision Chip Architecture for High-Resolution Line-of-Sight Detection Including Saccade

Although the line-of-sight (LoS) is expected to be useful as input methodology for computer systems, the application area of the conventional LoS detection system composed of video camera and image processor is restricted in the specialized area, such as academic research, due to its large size and high cost. There is a rapid eye motion, so called 'saccade' in our eye motion, which is expected to be useful for various applications. Because of the saccade's very high speed, it is impossible to track the saccade without using high speed camera. The authors have been proposing the high speed vision chip for LoS detection including saccade based on the pixel parallel processing architecture, however, its resolution is very low for the large size of its pixel. In this paper, we propose and discuss an architecture of the vision chip for LoS detection including saccade based on column-parallel processing manner for increasing the resolution with keeping high processing speed.

Vision Chip Architecture for Detecting Line of Sight Including Saccade

Rapid eye motion, or so called saccade, is a very quick eye motion which always occurs regardless of our intention. Although the line of sight (LOS) with saccade tracking is expected to be used for a new type of computer-human interface, it is impossible to track it using the conventional video camera, because of its speed which is often up to 600 degrees per second. Vision Chip is an intelligent image sensor which has the photo receptor and the image processing circuitry on a single chip, which can process the acquired image information by keeping its spatial parallelism. It has also the ability of implementing the very compact integrated vision system. In this paper, we describe the vision chip architecture which has the capability of detecting the line of sight from infrared eye image, with the processing speed supporting the saccade tracking. The vision chip described here has the pixel parallel processing architecture, with the node automata for each pixel as image processing. The acquired image is digitized to two flags indicating the Purkinje's image and the pupil by comparators at first. The digitized images are then shrunk, followed by several steps of expanding by node automata located at each pixel. The shrinking process is kept executed until all the pixels disappear, and the pixel disappearing at last indicates the center of the Purkinje's image and the pupil. This disappearing step is detected by the projection circuitry in pixel circuit for fast operation, and the coordinates of the center of the Purkinje's image and the pupil are generated by the simple encoders. We describe the whole architecture of this vision chip, as well as the pixel architecture. We also describe the evaluation of proposed algorithm with numerical simulation, as well as processing speed using FPGA, and improvement in resolution using column parallel architecture.

Higher Order Autocorrelation Vision Chip

This paper describes very large scale integration implementation using a new vision chip architecture specialized for target tracking and recognition. A 64 <tex xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">$times$</tex> 64 pixel prototype vision chip and its evaluation results are shown. The extraction algorithms of both higher order local autocorrelation (HLAC) features and moment features are implemented on the prototype chip in order to achieve high-speed image processing and enhanced pixel integration. The chip is integrated on a 5.00 mm <tex xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">$times$</tex> 5.00 mm chip using a 0.35- <tex xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">$muhboxm$</tex> CMOS DLP/TLM process; the pixel size is <tex xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">$hbox44.2 muhboxm times hbox48.3 muhboxm$</tex> . The maximum current consumption is approximately 400 mA, and the chip can calculate all HLAC features more than 26 times in 1 ms. The experimental results also demonstrate that the chip can successfully recognize and count high-speed objects at real time.

３２×３２画素キャパシティブフィードバックリセット型パルス周波数変調方式低電圧ビジョンチップの試作と評価

We fabricated a low-voltage 32×32-pixel pulse-frequency-modulation vision chip with an image processing function executed in a pulse domain in a standard 0.35-μm CMOS technology. We showed the characteristics and feasibility of our vision chip architecture.

A digital vision chip specialized for high-speed target tracking

This paper describes a new vision chip architecture for high-speed target tracking. The processing speed and the number of pixels are improved by hardware implementation of a special algorithm which utilizes a property of high-speed vision and introduction of bit-serial and cumulative summation circuits. As a result, 18 objects in a 128 /spl times/ 128 image can be tracked in 1 ms. Based on the architecture, a prototype chip has been developed; 64 /spl times/ 64 pixels are integrated in 7 mm square chip and the power consumption for obtaining the centroid of an object per every 1 ms is 112 mW. Some experiments are performed on the evaluation board which is developed for evaluation under the condition of actual operation. High-speed target tracking including multitarget tracking with collision and separation has successfully been achieved.

2P2-G01 ポリゴンマッチングビジョンチップのアーキテクチャ設計

本稿では, ポリゴン図形を用いたテンプレートマッチングを高速に実現可能とするビジョンチップアーキテクチャを提案し, その論理シミュレーション結果を示す。提案するアーキテクチャでは, ポリゴンマッチングを行う上で重要となるax+by+c>0の直線領域描画操作における完全画素並列による処理を, xに依存したax+c, yに依存した-byとのビットシリアル比較のみとすることにより, ポリゴンマッチング演算の高集積化かつ高速性の両立を実現している。

Self windowing for high‐speed vision

With high-speed vision systems such as vision chips that support frame rates much higher than video signal (NTSC 30 Hz), image variation is small from frame to frame. Using this feature of high-speed vision, various image processing algorithms can be simplified. In particular, this paper proposes the Self Windowing algorithm for image segmentation and matching. Operability of the proposed algorithm was validated experimentally on S3PE vision chip architecture. © 2001 Scripta Technica, Syst Comp Jpn, 32(10): 51–58, 2001

Self windowing for high‐speed vision

AbstractWith high‐speed vision systems such as vision chips that support frame rates much higher than video signal (NTSC 30 Hz), image variation is small from frame to frame. Using this feature of high‐speed vision, various image processing algorithms can be simplified. In particular, this paper proposes the Self Windowing algorithm for image segmentation and matching. Operability of the proposed algorithm was validated experimentally on S3PE vision chip architecture. © 2001 Scripta Technica, Syst Comp Jpn, 32(10): 51–58, 2001

Vision chip architecture with light adaptation mechanism

Light adaptive algorithms/architectures are proposed for regularization vision chips. The adaptation mechanisms allow the regularization parameters to change in an adaptive manner in accordance with the light intensity of given images. This is achieved by adaptively changing the conductance values associated with massively parallel resistive networks. The algorithms/architectures are inspired by the adaptation mechanisms of the retinal horizonal cells of the lower vertebrates.

General-purpose vision chip architecture for real-time machine vision

To solve the I/O bottleneck problem in existing vision systems and to realize versatile processing adaptive to various and changing environments, we propose a new vision chip architecture for applications such as robot vision. The chip has general-purpose processing elements (PEs) with each PE being directly connected to a photo detector (PD) and can implement various visual processing algorithms. We developed and simulated some sample programs for the chip and proved that they can be processed within 1 ms/frame, a rate that is high enough for high-speed visual feedback for robot control. Aiming to complete the chip, we are now developing test chips based on the architecture. The latest design has 8 x 8 PEs and PDs in an area 3.3 mm x 3.0 mm using a 0.8 μm CMOS process.