Virtual Substrate Research Articles

Compositionally graded Ga1−xInxP buffers grown by static and dynamic hydride vapor phase epitaxy at rates up to 1 μm/min

We demonstrate Ga1−xInxP compositionally graded buffers (CGBs) grown on GaAs with lattice constants between GaAs and InP by hydride vapor phase epitaxy (HVPE). Growth rates were up to ∼1 μm/min, and the threading dislocation density (TDD) was as low as 1.0 × 106 cm−2. We studied the effect of the substrate offcut direction, growth rate, and strain grading rate on the CGB defect structure. We compared the effect of a “dynamic” grading style, which creates compositional interfaces via mechanical transfer of a substrate between two growth chambers, vs “static” grading where the CGB grows in a single chamber. Dynamic grading yielded smoother grades with higher relaxation, but TDD was not significantly different between the two styles. The substrate offcut direction was the most important factor for obtaining CGBs with low defect density. (001) substrates offcut toward (111)B yielded smoother CGBs with lower TDD compared to CGBs grown on substrates offcut toward (111)A. Transmission electron microscopy of static and dynamic CGBs grown on A- and B-offcuts only found evidence of phase separation in a static A-offcut CGB, indicating that the B-offcut limits phase separation, which, in turn, keeps TDD low. Reductions in growth rate led to the appearance of CuPt-type atomic ordering, which affected the distribution of dislocations on the active glide planes but did not alter TDD significantly. Higher growth rates led to smoother CGBs and did not appreciably increase TDD as otherwise predicted by steady-state models of plastic relaxation. These results show HVPE's promise for lattice-mismatched applications and low-cost InP virtual substrates on GaAs.

Crystal polarity discrimination in GaN nanowires on graphene

We present experimental data and computational analysis of the formation of GaN nanowires on graphene virtual substrates.

Continuous-Wave Magneto-Optical Determination of the Carrier Lifetime in Coherent Ge1−xSnx/Ge Heterostructures

We present a magneto-optical study of the carrier dynamics in compressively strained Ge(1-x)Sn(x) films having Sn compositions up to 10% epitaxially grown on blanket Ge on Si (001) virtual substrates. We leverage the Hanle effect under steady-state excitation to study the spin-dependent optical transitions in presence of an external magnetic field. This allowed us to obtain direct access to the dynamics of the optically-induced carrier population. Our approach singled out that at cryogenic temperatures the effective lifetime of the photogenerated carriers in coherent Ge(1-x)Sn(x) occurs in the sub-ns time scale. Supported by a model estimate of the radiative lifetime, our measurements indicate that carrier recombination is dominated by non-radiative processes. Our results thus provide central information to advance the fundamental understanding of carrier kinetics in this novel direct-gap group-IV material system. Such knowledge can be a stepping stone in the quest for the implementation of Ge(1-x)Sn(x)-based functional devices.

Perspective on advances in InAsSb type II superlattices grown on virtual substrates

Metamorphic InAs1−xSbx/InAs1−ySby strained layer superlattice (SLS) structures allow for great flexibility of engineering artificial band structures and, therefore, the design of new optical and electrical properties. By using tailored virtual substrates, the average lattice constant of the SLS can be chosen anywhere between 0.606 nm (InAs) and 0.648 nm (InSb), which allows for flexibility in the choice of compositions and thicknesses of the constituent layers. These parameters can then be tuned in a wide range, which is not possible when using binary substrates. Specifically, the layer thicknesses can be nearly arbitrarily small. Short period InAs1−xSbx/InAs1−ySby SLSs exhibit strong optical absorption and improved perpendicular carrier transport and can demonstrate Dirac-type carrier dispersion, a large g-factor, and deep band inversion. The prospects for the development of devices based on these structures are discussed.

Effect of Defects on the Performance of Si-Based GeSn/Ge Mid-Infrared Phototransistors

In this paper, we discuss the impact of interfaces and defects on the frequency performance of Si-based GeSn heterojunction phototransistors (HPTs) at room temperature. Furthermore, the effect of base-emitter (B-E) voltage on the spectral responsivity (SR) and detectivity (D*) has also been studied. The presented device consists of Ge <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">1-x</sub> Sn <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">x</sub> alloy in the active layer to enhance the photodetection range. However, increasing Sn content in Ge <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">1-x</sub> Sn <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">x</sub> causes a lattice mismatch between Ge <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">1-x</sub> Sn <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">x</sub> and Ge virtual substrate (VS), which may increase defect density at the heterointerfaces. As a result, the diffusion length (L <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">p</sub> ) and minority carrier lifetime (τ <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">p</sub> ) may decrease, thereby, degrading the performance of the device. Three major noise components such as shot noise current components at the base-emitter (B-E) and base-collector (B-C) junctions and Johnson noise have been considered for the first time to calculate the detectivity and noise-equivalent-power (NEP) of the presented device. The calculated results show that the decrease in diffusion length does not cause a significant impact on the SR, D* and internal quantum efficiency (IQE), however, it significantly degraded the cut-off frequency (f <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">T</sub> ), maximum frequency (f <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">max</sub> ), and sensitivity (S) of the GeSn HPT at 300 K.

Controlling the relaxation mechanism of low strain Si1−xGex/Si(001) layers and reducing the threading dislocation density by providing a preexisting dislocation source

Strain relaxed Si1−xGex buffer layers on Si(001) can be used as virtual substrates for the growth of both strained Si and strained SiGe, which are suitable materials for sub-7 nm CMOS devices due to their enhanced carrier mobility. For industrial applications, the threading dislocation density (TDD) has to be as low as possible. However, a reduction of the TDD is limited by the balance between dislocation glide and nucleation as well as dislocation blocking. The relaxation mechanism of low strain Si0.98Ge0.02 layers on commercial substrates is compared to substrates with a predeposited SiGe backside layer, which provides threading dislocations at the edge of the wafer. It is shown that by the exploitation of this reservoir, the critical thickness for plastic relaxation is reduced and the formation of misfit dislocation bundles can be prevented. Instead, upon reaching the critical thickness, these preexisting dislocations simultaneously glide unhindered from the edge of the wafer toward the center. The resulting dislocation network is free of thick dislocation bundles that cause pileups, and the TDD can be reduced by one order of magnitude.

Thermal Stability at the Interface between Ferromagnetic Alloys and Germanium for Semiconductor Spintronics Devices

Spin MOSFET has drawn much attention as an attractive candidate for future semiconductor devices because of its nonvolatility and reconfigurability [1]. For realization of the spin MOSFET, highly efficient spin injection from ferromagnets to semiconductors with low parasitic resistance is one of the most important key technologies. Recently, we demonstrated room-temperature spin transport in germanium (Ge) based lateral spin valve devices with Schottky-tunnel contact, where the interface resistance at the ferromagnet/Ge is much smaller than that with conventional insulating tunnel barriers [2, 3]. However, when the thermal annealing was conducted to fabricate gate-stack structures for the spin MOSFET, the spin injection/detection efficiency was degraded due to the formation of reaction layers at the ferromagnetic alloys/Ge interface [4]. In this study, we explore the enhancement in the thermal stability of the ferromagnet/Ge interface and demonstrate room-temperature spin signals even for the lateral spin device annealed at 250 oC by an insertion of five Fe atomic layers between the ferromagnetic alloys and Ge.We fabricated lateral spin valve devices with Co2FeAl0.5Si0.5(CFAS)/Fe (5 atomic-layers)/Ge Schottky tunnel junction [Fig. 1(a)]. A 70-nm-thick phosphorus (P) doped Ge layer was grown on Ge/Si(111) virtual substrate at 350 oC as a spin transport layer by molecular beam epitaxy (MBE). On the P doped Ge layer, five Fe atomic layers and an epitaxial CFAS layer were formed using low temperature MBE. Beneath the ferromagnetic contacts, the P δ-doping with a thin Si layer was inserted to promote the tunnel conduction. The CFAS/Fe and δ-doped Ge layers were patterned into the contacts with 0.4 × 5.0 μm2 and 1.0 × 5.0 μm2, where the edge-to-edge distances between the CFAS/n+-Ge contacts are designed to be 0.45 μm. As a reference sample, a device without the Fe atomic layers was also fabricated. The devices with and without the Fe atomic layers were annealed at 250 oC in N2 atmosphere.Figures 1(b) and (c) show the nonlocal spin signals at 77 K for devices annealed at 250 oC without and with an Fe insertion, respectively, together with schematics of the CFAS/Ge and CFAS/Fe/Ge interfaces after the annealing. For the device without an Fe insertion [Fig. 1(b)], the spin signal is significantly degraded (~97 %) compared with the as prepared device, where the Ge out-diffusion causes the degradation of the spin injection/detection efficiency [4]. On the other hand, even after the annealing, clear hysteretic curves related to the magnetization states of the ferromagnetic injector and detector contacts can be observed for the device with an insertion of Fe atomic layers [Fig. 1(c)]. Although there is ~50 % decrease of the spin signal by the annealing, the magnitude of nonlocal spin signals is ~ 140 mΩ due to the significant improvement of the spin injection efficiency [5] and of the thermal stability of the CFAS/Fe/Ge interface. As shown in schematics of Figs 1(b) and 1(c), the inserted Fe atomic layers can suppress the Ge out-diffusion into CFAS and maintain the highly efficient spin injection. For the device with an Fe atomic insertion annealed at 250 oC, a spin signal of ~7 mΩ can be obtained even at room temperature.This work was partly supported by Grants-in-Aid for Scientific Research (A) (No. 16H02333) and (S) (No. 17H06120 and 19H05616) from the Japan Society for the Promotion of Science (JSPS). M.Y. acknowledges JSPS Research Fellowships for Young Scientists (No.18J00502).[1] S. Sugahara and M. Tanaka, Appl. Phys. Lett. 84, 2307 (2004).[2] M. Yamada et al., Appl. Phys. Express 10, 093001 (2017).[3] M. Tsukahara et al., Appl. Phys. Express 12, 033002 (2019).[4] B. Kuerbanjiang et al., Phys. Rev. B 98, 115304 (2018).[5] M. Yamada et al., (submitted). Figure 1

Capacitance-Voltage Measurements on MBE-Grown Ge-SixGe1-x-ySny Heterojunction pn-Diodes for Material Characterisation

In recent years, there has been an increased interest in the ternary Group-IV semiconductor alloy SixGe1-x-ySny [1–4]. Since it allows the decoupling of its bandgap and its lattice-constant, SixGe1-x-ySny is predestined for the realisation of lattice-matched heterojunctions on Ge(Sn) virtual substrates on the Si platform. Furthermore, SixGe1-x-ySny is a predicted direct bandgap semiconductor at higher Sn concentrations, which makes it attractive for optoelectronic applications. An exemplary heterojunction optoelectronic device would be the single confinement heterostructure laser diode, the still missing key component for the monolithic integration of the optical on-chip communication on Si.However, the design and dimensioning of heterojunction devices requires detailed knowledge of the electrical properties of the alloy semiconductor over composition, where currently much less is known about SixGe1-x-ySny. Although, previous investigations have focused mostly on the growth conditions and the optical properties of SixGe1-x-ySny bulk alloys [1,2,4].In this work, we will concentrate on the growth and electrical characterisation of Ge-SixGe1-x-ySny heterojunction diodes. In detail, we will highlight the possibilities of current-voltage (I-V) and capacitance-voltage (C-V) measurements on Ge-SixGe1-x-ySny heterojunction pn-diodes as a useful tool for material characterisation. For this purpose, we grew a series of four samples with different composition of the SixGe1-x-ySny layer, but the SixGe1-x-ySny composition fulfilling lattice-matching on Ge (see Fig 1 (a)). Afterwards, we fabricated single mesa diodes to enable the subsequent electrical characterisation of the grown heterostructure diodes.The growth process was performed in a 6” molecular beam epitaxy (MBE) system, where Si, Ge and Sn are used as matrix materials and B and Sb as dopants, respectively. Since the condition of lattice matched growth of SixGe1-x-ySny requires a fixed ratio of Si/Sn = 3.66, the Si and Sn fluxes were kept constant for all samples. Thus, we varied the Ge flux to achieve different SixGe1-x-ySny compositions, resulting in a varying SixGe1-x-ySny growth rate. This method enables better control of the lattice matching but also requires a highly precise calibration of the evaporation cells of the alloy compound fluxes. The Sn concentration of the SixGe1-x-ySny layers was varied between 5 % and 12.5 %. Since the most critical growth parameter is the substrate temperature, it is therefore measured and controlled in-situ by a thermocouple as well as an infrared pyrometer. Especially, the infrared pyrometer allows us to observe the dynamic processes on the sample surface during growth. For the growth of the SixGe1-x-ySny layer, we chose to keep the substrate temperature at TSub = 200 °C, which is mainly based on our previous SixGe1-x-ySny growth studies.The heterojunction pn-diode (see Fig 1 (a)) is formed by a p-doped Ge layer with an acceptor concentration of NA = 1018 cm-3 and the n-doped SixGe1-x-ySny layer with a donor concentration of ND = 5·1019 cm-3. In order to achieve a good ohmic contact to the p-Ge, a highly p-doped Ge layer forms the underlying bottom contact of the diode. The whole diode structure is grown on our standard Ge virtual substrate (VS) on Si(100) [5].A detailed material characterisation was performed to achieve information of the composition as well as the crystal quality using X-ray diffraction (XRD) and Raman spectroscopy.After MBE growth, the samples were processed to diodes in a single mesa process. For the subsequent I-V and C-V measurements, we used a Keithley 4200 semiconductor characterisation system using the bottom as signal and the top as ground contact (Fig 1 (b)). For the C-V measurements, a parallel capacitance (C) and conductance (G) model was applied. The maximum measurement frequency was f = 100 kHz. Fig. 1 (c) shows a comparison of the current density-voltage (J-V) characteristics of diodes with a mesa radius of 80 µm for all four compositions. As can be seen, good diode behaviour is achieved even for high Sn concentrations. An exemplary capacitance-voltage and conductance-voltage (C-V and G-V) characteristics of the sample with 10 % Sn is shown in Fig 1 (d). The C-V characteristics shows good agreement with the theoretical curve in the range of -0.6 V ≤ vDC ≤ 0 V. Further calculations in this range allowed us the extraction of the built-in-voltage of the heterojunction diode, an important parameter of a pn-heterojunction. We present detailed results of the C-V measurements of our diodes and the applied methods for material characterisation.Our results show that C-V measurement of SixGe1-x-ySny heterojunction pn-diodes is a useful tool for the determination of electrical parameters of this novel ternary alloy semiconductor SixGe1-x-ySny. These parameters are crucial for the further design of SixGe1-x-ySny heterojunction devices. Figure 1

(Invited) Stress Simulations of Fins, Wires, and Nanosheets

As the scalability of FinFET architectures is stretched to its limits in the most advanced technologies, industry and research are looking to the next candidates to scale the gate lengths a few nanometers closer to 10nm. Nanosheets and nanowires are such candidates, and specifically the introduction of the former is considered by a major industry player [1]. The inflection point of the transition from fins to sheets and wires depends on multiple trade-offs, of which channel stress is one: stress in the new architectures should preferably match the one in fins to become a viable contender to FinFET technologies. The introduction of stress in fins, wires and sheets, including devices with alternative channel materials, has been studied by several excellent publications from others [2-5], as well as by us [6-8].This work will focus on TCAD simulations of channel stress in fins, wires and sheets with typical 5nm-node dimensions. We focus on stress generation resulting from the following interacting stressors: 1. Lattice mismatch stress resulting from a different Ge composition between the substrate and the channel 2. lattice mismatch stress between the source/drain regions and the substrate (and channel) 3. for the case of wires and sheets, lattice mismatch stress from the sacrificial layers that are grown in between the wires and sheets, and that are removed in the replacement gate module. All simulations are performed with Sentaurus Process [9].For Si0.5Ge0.5 nanowires on a Si0.75Ge0.25 virtual substrate (Fig. 1) with Si0.5Ge0.5 epitaxially grown source/drains, the longitudinal channel stress at the end of processing in the top, middle and bottom wires is plotted in Fig. 2, and compared to the stress in corresponding fin structures. The following observations can be made: 1. Compressive (i.e. negative) channel stress is found, making this configuration suitable for p-type devices. 2. stresses are strongly dependent on the original fin or wire length, as stress relaxation occurs during fin/ wire cut. 3. there is significant difference between the stress in the top, middle and bottom wire, especially for short wire lengths. 4. (absolute) stresses in wires are higher than in fins, thanks to the presence of the sacrificial layers that limit stress relaxation in wires during wire cut [6].Scaling the devices from 8nm-node to 3nm-node dimensions decreases the absolute stress in fins and wires, Fig. 3. However, significant stress values are predicted down to the smallest nodes, especially for nanowires (> 1GPa). For all nodes, the stress in wires outperforms the one in fins by 50-70%.Fig. 4 shows the channel stress in nanowires and sheets versus device width. Moving from wires (i.e. a device width of 7nm) to larger widths, corresponding to sheets, tends to decrease the volume ratio of the source/drain stressor to the channel. As a consequence, lower absolute stresses are predicted for wider sheets, even when the wire/sheet pitch is scaled along with the device width. In general the highest stresses are found when the channels are thin, provided the mechanical stability of the channel is not compromised, which is something that has not been assessed in this work.Finally, the goal of this work is to study one particular concern for source/drain epitaxy in nanowires and nanosheets: in the presence of internal spacers, the source/drain epi starts from the nanowires as well as from the substrate, and may not join perfectly, leading to stress loss (Fig. 5). This work will perform a worst-case estimate of the stress loss in the presence of various defective interfaces. The TCAD results will be compared with experimentally measured strain using nano-beam diffraction [7-8].

(Invited) Strain Engineering of Si/Ge Heterostructures on Ge-on-Si Platform

Si/Ge heterostructures with high Ge contents have attracted increasing interests for last few decades because of their various high potential applications in the microelectronics industry. Strain engineering is an additional key technology not only for electronic devices with enhanced carrier mobilities but also for photonic devices since efficient light emission can be made possible via strain-induced direct band transition. In addition to the conventional (100) orientation, Si/Ge with a (111) orientation is very attractive owing to the higher electron mobility and applicability to spintronic devices via lattice matched epitaxial growth of high-quality ferromagnetic materials.As well known, however, it is a challenging issue to grow high-quality Ge-rich SiGe layers on the Si platform due to the large lattice mismatch between Si and Ge. Hence, strain engineered Si/Ge heterostructures with high Ge contents have to be created on Ge-on-Si virtual substrates, whereas strain states and crystallinities of the SiGe are expected to be highly influenced by those of the Ge-on-Si. Here, we show recent studies on heteroepitaxy of various Si/Ge heterostructures on Ge-on-Si with various surface orientations and discuss their strain states, stabilities, critical thickness and crystal qualities. Furthermore, their applications to optoelectronic and spin devices are overviewed.

(Invited) Germanium-Tin Based Nano-Electronic and Photonic Devices

1. Introduction Germanium-Tin (Ge1-x Sn x ) alloy has many attractive properties that make it promising for many applications in nano-electronic and photonic devices and systems. GeSn has both higher hole and electron mobilities than Ge and Si to possibly enable scaling of the supply voltage for future high performance field-effect transistors (FETs). In addition, the tunable bandgap of GeSn by changing Sn compositions helps to extend the photo detection range beyond what can be achieved by Ge, covering wavelength larger than 1.55 µm.In this paper, we discuss the research and development of utilizing GeSn for various applications in nano-electronic and photonic devices. This includes multi-gate GeSn p-channel FETs (pFETs) on GeSn-on-insulator (GeSnOI) substrates, realization of ultra-low contact resistivity by incorporation Sn into Ge for the metal/GeSn S/D contact, and GeSn photodetectors for applications at 2 µm wavelength range. 2. GeSn pFinFETs with Sub-10 nm Fin Width on GeSnOI Substrates Large-area GeSnOI substrates were fabricated using direct wafer bonding (DWB) and layer transfer techniques at a 200 mm wafer scale [1]. This GeSnOI substrate, together with the multi-gate architecture, enabled the realization of high performance Ge1-x Sn x p-FETs with ultra-scaled channel length down to 50 nm [2]. An optimized try etch process was developed to fabricate GeSn FinFETs with fin width less than 10 nm. Excellent electrical characteristics were achieved with subthreshold swing of 63 mV/decade, intrinsic transconductance of 900 µS/µm at VDS of -0.5 V, and high-field effective mobility of 275 cm2/V·s. 3. Metal/ GeSn p-type Contact with Ultra-low Contact Resistivity. GeSn has a smaller hole Schottky barrier and a hole effective mass (mh ) as compared to Ge. These advantages make GeSn attractive for low-resistance p-type contacts. In-situ Ga doping was introduced during the epitaxial growth of GeSn using molecular-beam epitaxy (MBE) and more than 50% reduction of specific contact resistivity ρc has been observed by incorporation of 5% Sn into Ge [3]. Further optimization of GeSn doping process by surface segregation or cold implantation reduces ρc of Ti/p+-GeSn to sub-10-9 Ω-cm2 regime [4]. The ultra-low ρc of Ti/p+-GeSn is retained after anneal at 420 oC for 1 hour, showing adequate thermal stability for BEOL process in current CMOS technology [5]. 4. GeSn Photo-detectors for Applications at 2 µm Wavelength Range High-speed photo detection was demonstrated beyond traditional telecommunication bands and reaching at 2 μm band, realized by GeSn/Ge multiple-quantum-well (MQW) photodiode on Si substrate [6]. GeSn/Ge MQW structure was employed to increase the critical thickness (hc ) of epitaxial GeSn on Ge virtual substrate. A decent responsivity of 15 mA/W was obtained at 2 μm. A low leakage current density of 44 mA/cm2 was achieved at reverse bias of 1 V, which is among the lowest reported values for all GeSn photodiodes. A 3-dB bandwidth (f 3-dB) larger than 10 GHz was experimentally demonstrated directly at 2 μm. Acknowledgment We would like to acknowledge the funding support from Singapore Ministry of Education Tier 2 grants (R-MOE2018-T2-1-137 and MOE2018-T2-2-154).[1] D. Lei et al., Appl. Phys. Lett., 109, 022106, 2016.[2] D. Lei et al., VLSI Symposia, 2018, 197-198.[3] Y. Wu et al., J. Appl. Phys., 122, 224503, 2017.[4] Y. Wu et al., VLSI Symposia, 2018, 77-78.[5] Y. Wu et al., IEEE Electron Device Lett., 40, 1575-1578, 2019.[6] S. Xu et al., IEDM, 2018, 544-547.

Analytical drain current model of strained junctionless nanowire tunnel field‐effect transistor fabricated on virtual substrate

This study proposes an analytical drain model of the strained junctionless nanowire tunnel field-effect transistor fabricated on the S i 1 − x G e x virtual substrate. The surface potential is derived by solving Poisson's equation in the channel region. Effects of the strained silicon on the potential profile can be expressed as a function of the Ge concentration in the S i 1 − x G e x virtual substrate. An analytical expression for the drain current is derived by using the tangent line approximation method. The strain induced in the device could reduce the effective tunnelling barrier significantly, resulting in a larger band-to-band tunnelling generation rate and, therefore, higher drive current compared with the unstrained device. Impacts of device parameters such as the channel diameter, gate oxide thickness and gate dielectric constant on the device performance are investigated. Results of the proposed model are verified by comparing with the device simulator.

Effect of Cd/As flux ratio and annealing process on the transport properties of Cd3As2 films grown by molecular beam epitaxy

To study how the Cd/As flux ratio affects the microstructure and transport properties for Cd3As2 films, we used molecular beam epitaxy (MBE) to grow Cd3As2 (224) thin films on CdTe (111)/GaAs (001) virtual substrates. The effects of Cd/As flux ratio, during the grown process, on the electrical properties and surface morphology of the sample was studied. The films grown at lower Cd/As flux ratio have higher electron mobility and longer effective dephasing length. With decreasing Cd/As flux ratio, the magnetoresistance (MR) of the film changes from negative to positive. These results show that a lower beam ratio is beneficial to improve the crystal quality. In order to optimize the electrical properties of the films, the effect of annealing on the electron mobility and MR have been studied. After annealing, the MR changes from negative to positive, the electron mobility increase by 8 times, and the MR increase from 15% to 360% at 9 T. These results indicate that annealing is an effective method to optimize the electrical properties of Cd3As2 epitaxial films.

Structural-spectroscopic study of epitaxial GaAs layers grown on compliant substrates based on a superstructural layer and protoporous silicon

A new type of virtual (compliant) substrate based on a superstructural AlGaAs layer (SL) and a layer of protoporous silicon (proto-Si) formed on c-Si was used for the low-temperature MOCVD growth of structurally perfect epitaxial GaAs films. The introduction of SL into the compliant substrate in addition to proto-Si eliminated several negative effects associated with the low-temperature growth, diminishing the stress level in the epitaxial layer, protecting this layer from autodoping with silicon atoms, reducing the number of technical procedures associated with the growth of the intermediate buffer layer, improving the structural and morphological properties of the epitaxial layer, as well as providing good optical characteristics. This study contributes to the understanding of the fundamentals of physics and technology of the integrated (III-V)/Si heterostructures by developing their potential for application in optoelectronic devices.

Mid-infrared type-II InAs/InAsSb quantum wells integrated on silicon

Direct integration of III–V semiconductor light sources on silicon is an essential step toward the development of portable, on-chip infrared sensor systems. Driven by the presence of characteristic molecular fingerprints in the mid-infrared (MIR) spectral region, such systems may have a wide range of applications in infrared imaging, gas sensing, and medical diagnostics. This paper reports on the integration of an InAs virtual substrate and high crystalline quality InAs/InAsSb multi-quantum wells on Si using a three-stage InAs/GaSb/Si buffer layer. It is shown that the InAs/GaSb interface demonstrates a strong dislocation filtering effect. A series of strained AlSb/InAs dislocation filter superlattices was also used, resulting in a low surface dislocation density of approximately 4 × 107 cm−2. The InAs/InAsSb wells exhibited a strong photoluminescence signal at elevated temperatures. Analysis of these results indicates that radiative recombination is the dominant recombination mechanism, making this structure promising for fabricating MIR Si-based sensor systems.

Epitaxial Ge-on-Nothing Virtual Substrates for 3D Device Stacking Technologies

Future monolithic heterogeneous integration of Ge and IIIV materials in electronic, optoelectronic and photonic devices requires advanced layer transfer and 3D device stacking technologies, which starts with the fabrication of suitable (virtual) substrates. A layer transfer process based on the reorganization of macro-porous Si at high temperature was developed by imec [1]. The developed fabrication scheme to fabricate macropores is based on standard UV lithography and dry etching techniques rather than electrochemical etching. This enables an easy transfer to full Si wafers (up to 300 mm). During a high-temperature step, the top part of the macro-porous Si reflows. By using proper anneal conditions, the layer detaches from the mother substrate, being anchored by a few attachment points only, forming a ‘Si on nothing’ (SoN) stack (Fig. 1a). The suspended Si layer can then easily be transferred to another substrate.In this contribution, we assess the suitability of macro-porous Si and SoN as starting material for Ge virtual substrates. The goal is to provide a fabrication scheme that allows an easy detachment of the virtual substrate after wafer to wafer bonding. Macro-porous Si was only fabricated in the inner 10x10 cm2 area of 200 mm wafers using imec’s qualified fabrication scheme. Ge layers were simultaneously grown on the inner macro-porous Si (or SoN) and the outer bulk Si. This allows to compare the material properties without the risk of wafer to wafer variations due to non-reproducibility issues. Our approach for making macro-porous Si and SoN provides mono-crystalline, nearly defect-free, and extremely smooth Si starting surfaces. A standard low temperature epitaxial Ge growth process in an ASM-Epsilon® 2000 system was used to deposit the Ge layers [2].As an example, Fig. 1b shows a 1.25 mm thick mono-crystalline epitaxial Ge layer grown on a macro-porous Si layer. The Ge growth proceeds in a 2-dimensional mono-crystalline growth mode. The surface morphology of the grown Ge is not affected by the starting surface (Fig. 1c,d). The Full Width at Half Maximum (FWHM) as extracted from w-2q High Resolution X-ray Diffraction scans acquired around the Ge (004) Bragg peak is strongly reduced after a post Ge deposition anneal, which was also reported for Ge on bulk Si [2]. Threading dislocations annihilate during the post-epi anneal. FWHM values as low as 160 arc sec have been measured for 1.25 mm thick Ge layers independent of the underlying layer. This reflects the high material quality of the grown Ge. The difference in thermal expansion coefficient between Si and Ge results in some tensile stress in the annealed Ge layer, which explains the well-known shift in XRD peak position. The improvement in material quality by using a post-epi anneal is also reflected in the carrier lifetime as extracted from room-temperature photoluminescence measurements. The carrier lifetime increases from <0.2 ns (as-grown layers) to 3.3 ns and 3.6 ns for Ge on porous Si and bulk Si, respectively. The TDD, as extracted from ECCI measurements, was identical for both parts of the Si wafer (2-4e7 cm-2) and close to the values expected from literature. The material properties listed above are not affected by the thickness of the closed Si layer in-between the Ge and the porous Si.In conclusion, we developed a fabrication scheme for strain-relaxed Ge grown on SoN (or on macroporous Si) starting from conventional Si substrates. The material properties of the virtual Ge substrate are identical to those obtained for Ge grown on bulk Si. The virtual substrate serves as starting material for layer transfer and 3D device stacking technologies. The fabrication scheme can be extended to (defect free) bulk Ge for which the fabrication of Ge on nothing followed by layer transfer has been demonstrated [3].

Si-matched BxGa1−xP grown via hybrid solid- and gas-source molecular beam epitaxy

The growth of BxGa1−xP alloys by hybrid solid/gas-source molecular beam epitaxy, with B supplied via the BCl3 gas precursor, is demonstrated. Compositional control ranging from pure GaP to B0.045Ga0.955P has thus far been achieved. Slightly tensile-strained B0.031Ga0.969P grown on nearly pseudomorphic, compressively strained GaP/Si was used to produce an effectively strain-free (0.06% tensile misfit at growth temperature) 160 nm total III–V thickness BxGa1−xP/Si virtual substrate with a threading dislocation density of &amp;lt;3 × 105 cm−2, at least 4× lower than comparable GaP/Si control samples. Cross-sectional transmission electron microscopy reveals that subsequent GaP overgrowth undergoes epilayer relaxation via dislocation introduction and glide at the upper GaP/B0.031Ga0.969P interface, rather than the lower GaP/Si interface, confirming the strain-balanced nature of the B0.031Ga0.969P/GaP/Si structure and its potential use as a III–V virtual substrate.

Effect of sintering germanium epilayers on dislocation dynamics: From theory to experimental observation

High-quality germanium epilayers on Si with low threading-dislocation density were achieved by sintering of porous Ge/Si films. The process consists in the formation of porous Ge nanostructures by dislocation-selective electrochemical etching of Ge/Si films, followed by high-temperature treatment to generate a monocrystalline, voided Ge layer that intercepts dislocations and prevents them from propagating to the sample surface. In this work, we model the morphological changes that occur during the thermal treatment-induced surface diffusion of an axially symmetric hole. Simulations and experiments show individual large spherical voids, aligned along the dislocation core. The creation of voids could facilitate interactions between dislocations, enabling the dislocation network to change its connectivity in a way that facilitates the subsequent annihilation of dislocation segments. This confirms that thermally activated processes such as state diffusion of porous materials provide mechanisms whereby the defects are removed or arranged in configurations of lower energy. This demonstration paves the way to develop a virtual substrate on many other heterostructures for potential applications in integrated photonic and optoelectronic devices.

Capturing the Effects of Free Surfaces on Threading Dislocation Density Reduction

The big concern with using silicon as a substrate for making Ge and III-V devices is the dislocation density in the epilayers. Dislocations degrade device performance by trapping the photo-generated carriers, dragging down efficiency. In this manuscript, a Ge/Si substrate is treated with a post epitaxial process to create a region with a high density of nanovoids within the Ge/Si structure, which acts as a free surface that attracts dislocations, facilitating the subsequent annihilation of their threading arms. Nanovoids are formed in the Ge layer by electrochemical porosification, followed by thermal annealing, creating a new configuration referred to as nanovoid-based Ge/Si virtual substrate (NVS).

Epitaxial Ge-on-Nothing Virtual Substrates for 3D Device Stacking Technologies

We introduce a fabrication scheme for strain-relaxed Ge, epitaxially grown on a Si-on-Nothing (SiON) template formed from macro-porous Si. The SiON template is fabricated on regular Si substrates using conventional lithography, dry-etching and annealing routines. The material properties of the virtual Ge substrate grown on this detachable template are identical to those obtained for Ge grown on bulk Si. Strain-relaxed, suspended, and detachable Ge-on-Nothing (GeON) was fabricated using a similar fabrication scheme except for the epitaxial growth of Ge on Si, which was performed before the patterning of the substrate. For GeON, the extracted excess carrier lifetime using time-resolved photoluminescence (32 ns) was > 4 times higher than the values measured for Ge grown on bulk Si with a similar thickness of the Ge layer. Both templates can be considered as starting material for layer transfer and 3D device stacking technologies provided that successful detachment from the parent substrate can be demonstrated.