Virtual Field Programmable Gate Arrays Research Articles

Using data-mining techniques to improve combinatorial optimization algorithms

In this work, we show how data-mining can be used to cluster algorithmic generated data and use that data to improve algorithms that solve combinatorial optimization problems for a real-world application—the field-programmable gate array placement problem. Our methodology is a means for other algorithm engineers to improve their own algorithms for specific real-world problems that are hard to improve. In our case, the placement algorithms are difficult to improve, and to find better heuristics we analyze the results of placement solutions to find clustered information which can then be used to improve the algorithms. Specifically, we show a technique for gathering cluster information about placement, we create a new simulated annealing algorithm and a new genetic algorithm that can deal with a mixed granularity of placement objects on a virtual field-programmable gate array, and we show that these algorithms either execute faster or improve the overall quality of solution compared to their basic algorithm without this clustering data and improved heuristics. For our improved simulated annealing placer we improve the algorithms run-time by 17% across a range of benchmarks, and our genetic algorithm improves placement metrics—-critical path by 10% and channel-width by 4%.

RETRACTED: Physical education image analysis based on virtual crowd simulation and FPGA

Physical Culture and Sports research are coordinated with the game (rational, educators, game director, and game theory from a specific or a general point) medicine sociology. They revolve around representatives, value theory, and modern games near parts. This journal is dedicated to humanists, social researchers, students, and practitioners, social analysts, research institutions, and professionals. To practice city models, company directors need to incorporate a large number of personnel for the legs, automobiles, and other powerful elements. Analysts use the same design of registration, i.e. more than 100 million long-distance race. To reproduce and become a member, they continue to be referring many inferences using the fluffy ground on the Graphical Process Unit (GPU). This is an element of PC Vision that is often used to extract the perspective of one of the computing where the histogram is used. Using this calculation requires a large amount of isolated bright spots in the image calculation. One approach, Adaptive speed from the games, for example to support calculations, a Field-Programmable GateArray (FPGA) is equal to the front door. First, an overview of the position and inclination calculation apparatus histogram is given. To implement the full classification, it only uses the equations of decision boundaries. This is to simplify the FPGA implementation through simple expressions, rather than the whole classification. At this point, will see how field-programmable front position has been used in the last decade, i.e. the slope of the histogram. The remainder of the beam is information including resolution, a large number of the task of the receptacle and the direction, progress, and standardized way of calculation. The third cluster is a first program which is a common computing device program, including the position angle dependence modemed histogram and highlights its execution apparatus implemented. The goal uses different pixel per clock cycle analysis and the asset uses the so-called fast measurement purposes. Finally, the speed and accuracy are calculated and present a summary indicator of the value of using the planned use of assets, and the ability to locate the image to the overall performance.

Oscillator without a combinatorial loop and its threat to FPGA in data centre

Virtual field-programmable gate array (FPGA) is an emerging technology to put multiple users in the same FPGA fabric with logical isolation. Security researchers have studied new threats in virtual FPGA and proposed attacks on the logical isolation by exploiting analogue natures of FPGA. These attacks use an oscillator comprising a combinatorial loop to have access to the analogue domain using digital components only. Interestingly, the system in the field prohibits a combinatorial loop by a design rule check. In this Letter, the authors study if prohibiting a combinatorial loop is sufficient to thwart the conventional attacks. They negatively answer the question by showing oscillators without a combinatorial loop. They also show how to detect and reject the proposed oscillators by a design rule check.

Platform Specific FPGA Based Hybrid Active Power Filter for Power Quality Enhancement

Abstract Elimination of harmonics by the use of power filters is required for power quality improvement; provides a wide area for the researchers to develop efficient power filters with improved control platforms. This paper motivates the implementation of the embedded control platform for better control of the power filters for faster elimination of harmonics. Although many embedded processors fascinates the implementation of the control techniques but finding the feasible platform is a great task. Software implementations are feasible for most of the power electronics converters but the hardware design with required digital hardware is a challenging task. The present paper deals with the development of the control technique for the Hybrid Active Power Filter with Xilinx System Generator Platform. The virtual FPGA (Field Programmable Gate Array) platform provided by the Xilinx System Generator has the ability to generate better switching signals for the control of the power filter to generate compensating signal for elimination of harmonics to maintain the power quality in the distribution lines. Experimental results obtained by the setup developed in the Power System Laboratory presents the effectiveness of the Embedded Platform. Various source voltage conditions also simulated and performance is verified for the developed Hybrid Active Power Filter.

An architecture and design tool flow for embedding a virtual FPGA into a reconfigurable system-on-chip

Virtual field programmable gate arrays (FPGA) are overlay architectures realized on top of physical FPGAs. They are proposed to enhance or abstract away from the physical FPGA for experimenting with novel architectures and design tool flows. In this paper, we present an embedding of a ZUMA-based virtual FPGA fabric into a complete configurable system-on-chip. Such an embedding is required to fully harness the potential of virtual FPGAs, in particular to give the virtual circuits access to main memory and operating system services, and to enable a concurrent operation of virtualized and non-virtualized circuitry. We discuss our extension to ZUMA and its embedding into the ReconOS operating system for hardware/software systems. Furthermore, we present an open source tool flow to synthesize configurations for the virtual FPGA, along with an analysis of the area and delay overheads involved.

BASIC SIGNAL PROCESSING SYSTEM DESIGN ON FPGA USING LMS BASED ADAPTIVE FILTER

Adaptive digital filter based on LMS algorithms widely used in the area of digital signal processing to iteratively estimate the statistics of an unknown signal. Design of an adaptive filter is based on three major computing elements namely multiplier, adder and delay unit torealize the Finite Impulse Response (FIR) filter. The filter weights( coefficient) of the FIR filter are adjusted automatically by Least Mean Square of the error so as to match the adapted output to the desired input. This paper explains the design of adaptive filter by two approaches. One is model based approach and other is Field Programmable Gate Arrays (FPGAs). The model based design approach is developed around MATLAB, SIMULINK and SYSTEM GENERATOR tools, which provide a virtual FPGA platform. Modern FPGA include the resources needed to design efficient filtering structures. The LMS algorithm has been implemented on CYCLONE II EP2C35F672C8 FPGA device, using ALTERA QUARTUS II development platform. The three major demonstrable applications cited in the present work are System Identification, Noise reduction and Echo cancellation.

Hardware Genetic Algorithm Optimization by Critical Path Analysis using a Custom VLSI Architecture

This paper propose a Virtual-Field Programmable Gate Array (V-FPGA) architecture that allows direct access to its configuration bits to facilitate hardware evolution, thereby allowing any combinational or sequential digital circuit to be realized.
 By using the V-FPGA, this paper investigates two possible ways of making evolutionary hardware systems more scalable: by optimizing the system’s genetic algorithm (GA); and by decomposing the solution circuit into smaller, evolvable sub-circuits. GA optimization is done by: omitting a canonical GA’s crossover operator (i.e. by using a 1+λ algorithm); applying evolution constraints; and optimizing the fitness function. 
 A noteworthy contribution this research has made is the in-depth analysis of the phenotypes’ CPs. Through analyzing the CPs, it has been shown that a great amount of insight can be gained into a phenotype’s fitness.
 We found that as the number of columns in the Cartesian Genetic Programming array increases, so the likelihood of an external output being placed in the column decreases. Furthermore, the number of used LEs per column also substantially decreases per added column.
 Finally, we demonstrated the evolution of a state-decomposed control circuit. It was shown that the evolution of each state’s sub-circuit was possible, and suggest that modular evolution can be a successful tool when dealing with scalability.