Virtual Address Space Research Articles

Software fault tolerance in architectures with hierarchical protection levels

The effect on software fault tolerance of hardware features such as hierarchical privilege levels (rings), the use of descriptors for memory protection, separated virtual address spaces, and ring crossings that enforce specific energy points is considered. A strategy that uses a separate programming layer, the recovery layer, to handle fault-tolerant aspects of process interactions is discussed. The recovery metaprogram (RPM) which monitors the run-time behavior of the application program and coordinates error detection, recovery, and reconfiguration, is examined, focusing on privilege levels, which provide protection against error propagation, RMP implementation, and conversations. The intel 80286 has been used as a sample implementation vehicle, but most of the discussion applies to any machine with a similar range of features. Extension to multiprocessor systems is indicated.< <ETX xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">&gt;</ETX>

A camac handler for RT-11

A CAMAC handler for the RT-11 extended memory monitor is described. It permits CAMAC programs to run as virtual jobs, thus exploiting the full power of the extended memory monitor. For example, two CAMAC programs, each using its maximum 32K word virtual address space, may run in foreground/background mode. A LAM synchronized and terminated general multiple action is introduced to minimize the operating system overhead.

Compile-time program restructuring in multiprogrammed virtual memory systems

An evaluation is made of a way to reduce the cost of program restructuring by having a compiler determine the program's packing in virtual address space from an analysis of its source code. Two features of this method are the duplication of code modules in virtual address space and the inline substitution of the code for a called procedure. This compile-time restructuring algorithm is evaluated using the instruction-only address traces from a collection of programs. In a simulation of a virtual memory system using disks as secondary storage devices, the method is not successful, since it leads to a higher optimum space-time execution cost than that of the unrestructured program. The algorithm did reduce program space-time execution cost for some arbitrarily chosen memory allocations smaller than the optimum. This could be useful in a multiuser, multiprogrammed environment.< <ETX xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">&gt;</ETX>

Attacking the process migration bottleneck

Moving the contents of a large virtual address space stands out as the bottleneck in process migration, dominating all other costs and growing with the size of the program. Copy-on-reference shipment is shown to successfully attack this problem in the Accent distributed computing environment. Logical memory transfers at migration time with individual on-demand page fetches during remote execution allows relocations to occur up to one thousand times faster than with standard techniques. While the amount of allocated memory varies by four orders of magnitude across the processes studied, their transfer times are practically constant. The number of bytes exchanged between machines as a result of migration and remote execution drops by an average of 58% in the representative processes studied, and message-handling costs are cut by over 47% on average. The assumption that processes touch a relatively small part of their memory while executing is shown to be correct, helping to account for these figures. Accent's copy-on-reference facility can be used by any application wishing to take advantage of lazy shipment of data.

Coherency for multiprocessor virtual address caches

A multiprocessor cache memory system is described that supplies data to the processor based on virtual addresses, but maintains consistency in the main memory, both across caches and across virtual address spaces. Pages in the same or different address spaces may be mapped to share a single physical page. The same hardware is used for maintaining consistency both among caches and among virtual addresses. Three different notions of a cache "block" are defined: (1) the unit for transferring data to/from main storage, (2) the unit over which tag information is maintained, and (3) the unit over which consistency is maintained. The relation among these block sizes is explored, and it is shown that they can be optimized independently. It is shown that the use of large address blocks results in low overhead for the virtual address cache.

Coherency for multiprocessor virtual address caches

A multiprocessor cache memory system is described that supplies data to the processor based on virtual addresses, but maintains consistency in the main memory, both across caches and across virtual address spaces. Pages in the same or different address spaces may be mapped to share a single physical page. The same hardware is used for maintaining consistency both among caches and among virtual addresses. Three different notions of a cache "block" are defined: (1) the unit for transferring data to/from main storage, (2) the unit over which tag information is maintained, and (3) the unit over which consistency is maintained. The relation among these block sizes is explored, and it is shown that they can be optimized independently. It is shown that the use of large address blocks results in low overhead for the virtual address cache.

Coherency for multiprocessor virtual address caches

A multiprocessor cache memory system is described that supplies data to the processor based on virtual addresses, but maintains consistency in the main memory, both across caches and across virtual address spaces. Pages in the same or different address spaces may be mapped to share a single physical page. The same hardware is used for maintaining consistency both among caches and among virtual addresses. Three different notions of a cache "block" are defined: (1) the unit for transferring data to/from main storage, (2) the unit over which tag information is maintained, and (3) the unit over which consistency is maintained. The relation among these block sizes is explored, and it is shown that they can be optimized independently. It is shown that the use of large address blocks results in low overhead for the virtual address cache.

V60 real-time operating system

This paper describes the requirements for 32-bit microprocessor real-time operating systems, design objectives and the implementation of the V60(∗)/V70(∗∗) Real-Time Operating System (RTOS) and its programming supports. (∗), (∗∗) V60 and V70 are trademarks of NEC Corporation. The V60/V70 RTOS is designed for NEC's 32-bit microprocessor series, V60 and V70. It provides real-time operation with a reliable task environment, a high-level intertask communication mechanism based on Ada(∗)'s rendezvous and fault tolerant capability. These functions are implemented efficiently using V60/V70's architectural feature, e.g. multiple virtual address space, ring level protection and context switching instructions. The RTOS is constructed from three separable modules, real-time kernel, file system and UNIX (∗∗) supervisor. This structure can cover a wide range of application from small embedded systems to large fault tolerant systems. A high-level language and system generation support tools are also provided to increase application program productivity. (∗) Ada is a registered trademark of U.S. Government, Ada Joint Program Office. (∗∗) UNIX is a trademark of AT&T Bell Laboratories.

Distributed garbage collection

There are two basic approachs to the problem of storage reclamation, process- and processor-based, named for the view point used to recognize when a particular piece of storage can be reclaimed. Examples of the processor approach include mark/sweep and copying algorithms and their variants, while reference counting schemes use a process view of the collection. It is argued that the process approach is better suited for distributed computation where links between dynamically allocated objects may cross processor boundaries. In addition, the process approach allows the heap to be more conveniently shared with other processes in those cases when different processes might not have their own virtual address spaces. A new algorithm using the process approach is given. Its space requirement per object is better than that for reference counting. In addition, a restricted form of pointer replacement is supported which allows circular structures so constructed to be properly collected.

Reduced instruction set computers

Reduced instruction set computers aim for both simplicity in hardware and synergy between architectures and compilers. Optimizing compilers are used to compile programming languages down to instructions that are as unencumbered as microinstructions in a large virtual address space, and to make the instruction cycle time as fast as possible.

TheUNIXSystem: AUNIXSystem Implementation for System/370

This paper describes an implementation of the UNIX™ operating system for IBM System/370 computers. In this implementation an underlying Resident Supervisor, adapted from an existing IBM control program, provides machine control and multiprogramming; while a UNIX System Supervisor, adapted from the standard UNIX system kernel, provides the UNIX system environment. This implementation supports multiprocessing, paging, and large-process, virtual address spaces. Terminal handling is done through an outboard terminal processor. This paper describes the software structure, with emphasis on unique aspects of this implementation: multiprocessing and process synchronization, process creation, and outboard terminal handling. Capacity and performance of the UNIX system on large mainframes is also discussed. The first and principle user of the UNIX system for System/370 is the development project for the 5ESS™ switching system. This paper also discusses the use of a large mainframe UNIX system for this development. Included in this discussion are the reasons for selecting this system for development, applications software porting, and general experience with mainframe UNIX systems.

Virtual memory management for database systems

Over the last several years, a number of hardware and software systems have been developed which map entire files directly into the virtual memory address spaces used by programs. Since all file contents are directly addressable, there is no need for a programmer to issue explicit file system actions, such as Read or Write. In addition, all of the buffer management problems are eliminated, since programmers do not have to squeeze pieces of large files into small virtual spaces. Although these advantages are tempting, we find that database systems have gone their own way. In this paper, we will look at two particular approaches to database system design, and see how (and why) they interface to file systems as they do. We will then look at the potential advantages and implications of working more closely with virtual memory management, and describe some of the functions and constraints that would have to be supported by a generalized page manager.

Professional Workstations (Panel Session)

Andries van Dam The panel will examine the evolution of the professional workstation from a time shared terminal to powerful graphics-based personal computer connected to a resource-sharing local network. The panelists will speculate on the future evolution of both the hardware/software architecture and end user environment. Workstation development at Stanford James H. Clark Workstation development at Stanford is closely linked with graphics, distributed systems and networking. Two distinct systems have evolved over the last 3 years: the SUN system and the IRIS system. The SUN is a low-cost system based upon an efficient MC68000 processor/memory design and a relatively low-performance, high-resolution bit-map display. The IRIS (Integrated Raster Imaging System) is based upon the same MC68000 design, but the graphics part of the system is a modest- to low-cost, high-performance, high-resolution, color or black and white system that uses the Geometry Engine and several other custom IC parts. Both SUN and IRIS interface to the Stanford Ethernet network, and both are being used for distributed systems research, VLSI design stations, and graphics research. In addition, IRIS will probably be used for mechanical CAD research by the mechanical engineering department and in situations where high-performance graphics is important. Improvement Goals for Workstation Facilities Robert M. Dunn Three major areas of improvement are needed: interaction techniques that are simpler, provide faster reaction, are useful for higher-level inputs, and have user-style-oriented alternatives. The second area is for image rendering based on local capabilities, in varying degrees of image quality as a function of desired “grade of service”. The third area is to provide support to incremental model construction and approximate design evaluation. There must be evaluation techniques that can work on partial models and give one approximate results. Implications of these criteria for workstation architecture will be discussed. The application of network workstations to large-scale engineering Harvey Kriloff The development of computerized analysis procedures during the last twenty years has been largely oriented toward providing increased analytic function. This has meant that considerations of user access to specific capabilities or ease of use of these mammoth programs are only now becoming user concerns. The emerging new technologies for display, input and their interaction, when applied to the professional workstation, will be playing an increasingly important role in satisfying these concerns. A professional workstation can be used both to improve the efficiency by which data is collected for an existing analysis program and to assist the user in the preparation of data for a formal presentation or report. This performance improvement can be accomplished through the development of user-adapted “macro procedures” for data entry, the execution of processes to check program input data for accuracy and consistency, and workstation assistance in the training of both new and existing users. At the output stage of analysis, the workstation can be used to select and reformat information prepared by the analysis program, explore the interrelationship of results from several different analyses, and derive the data for a succeeding analysis in an iterative design mode. At Boeing Computer Services, we have been exploring the benefits realized by the development of such a workstation when applied to the field of structural engineering. An interaction-rich workstation with a human-engineered executive that controls and integrates the user interface, connected to our national network of IBM, CDC and CRAY computers with a broad variety of engineering software, supplies the engineer with a full range of tools for analysis, data preparation, report writing and data relationship exploration that are only beginning to be appreciated. In the next few years it is expected that this workstation (distributed) methodology for doing engineering and other quantitative professional functions will radically change the way these analytical processes are performed. Personal Workstations in a Local Network David Nelson For many applications, personal workstations provide a superior form of computing compared to timesharing. The requirements of workstations, however, go well beyond the facilities provided by the local computer; they must include the equivalent advantages of timesharing such as user-to-user communications, shared programs and data files, shared peripherals, etc. The preferred way to implement these functions is to interconnect all workstations by means of a high-speed local network, controlled by a distributed operating system which provides transparent access to all network resources through a network-wide virtual memory system. Additional workstation functions such as large virtual address space and a concurrent multiple-window display system significantly increase user productivity. A high resolution bit-map display system with hardware support for dynamics is an essential component. For the future we look towards both significant cost reductions and improvement in performance, as well as significantly higher level software to better implement the user-computer interface.

Design Trade-Offs in VAX-11 Translation Buffer Organization

A major feature of the VAX-11 is its large virtual address space. This trace-driven simulation scheme evaluates address translation hardware that supports this feature cost-effectively.

Solution of Large-Scale Sparse Least Squares Problems Using Auxiliary Storage

Very large sparse linear least squares problems arise in a variety of applications, such as geodetic network adjustments, photogrammetry, earthquake studies, and certain types of finite element analysis. Many of these problems are so large that it is impossible to solve them without using auxiliary storage devices. Some problems are so massive that the storage needed for their solution exceeds the virtual address space of the largest machines. In this paper we describe a method for solving such problems on a typical (large) computer and provide the results of some experiments illustrating the effectiveness of our approach. The method includes an automatic partitioning scheme which is essential to the efficient management of the data on auxiliary files.

A Pascal implementation of the GSPC Core Graphics package

A level 3 Pascal implementation is described of the original Core Graphics package proposed by the Graphics Standards Planning Committee of the ACM in 1977 [1]. The implementation was carried out as a team project by a group of final year Computing Science undergraduates, using a general-purpose mainframe (ICL 2976) with a large virtual address space. The available Pascal compiler recognised up to 32 significant characters in identifier names, which permitted the procedure names suggested in the specification to be used unmodified. The paper discusses the factors affecting the choice of language, the ease of use of the Core definition as a working document, and the success of the project both as an educational exercise and as an evaluation of the Core proposal.

New product applications: Three-chip, 32-bit mainframe has 1 terabyte virtual memory address space

New product applications: Three-chip, 32-bit mainframe has 1 terabyte virtual memory address space

Modular minicomputer with an associative stack and a virtual-addressing capability

The paper describes the design of a structured high-level-language minicomputer which is being designed and built at the University of Manchester. The design emphasis is on high performance and the machine incorporates a variable-length zero-address order code to provide a compact and efficient compiled code. The top elements of the stack are stored in a fast-access associative buffer which is also used to store frequently-used names and pointers. The buffer provides a powerful operand-accessing mechanism which overcomes most of the data-accessing and stack-organisational problems encountered by conventional stacking machines. A segmented virtual-address space is provided and the use of indirect orders enables this space to be extended to 24 bits, allowing large programs to be run. All address translation is performed by hardware to minimise overheads. Operating-system overheads are greatly reduced by storing frequently-used operands in the associative buffer and by providing hardware assistance for process changing and interrupt handling. Finally, flexibility and simplicity of design have been incorporated by adopting a modular approach and using a microprogram to implement the control at the block level.

Modular minicomputer with an associative stack and a virtual-addressing capability

The paper describes the design of a structured high-level-language minicomputer which is being designed and built at the University of Manchester. The design emphasis is on high performance and the machine incorporates a variable-length zero-address order code to provide a compact and efficient compiled code. The top elements of the stack are stored in a fast-access associative buffer which is also used to store frequently-used names and pointers. The buffer provides a powerful operand-accessing mechanism which overcomes most of the data-accessing and stack-organisational problems encountered by conventional stacking machines. A segmented virtual-address space is provided and the use of indirect orders enables this space to be extended to 24 bits, allowing large programs to be run. All address translation is performed by hardware to minimise overheads. Operating-system overheads are greatly reduced by storing frequently-used operands in the associative buffer and by providing hardware assistance for process changing and interrupt handling. Finally, flexibility and simplicity of design have been incorporated by adopting a modular approach and using a microprogram to implement the control at the block level.

An efficient, incremental, automatic garbage collector

This paper describes a new way of solving the storage reclamation problem for a system such as Lisp that allocates storage automatically from a heap, and does not require the programmer to give any indication that particular items are no longer useful or accessible. A reference count scheme for reclaiming non-self-referential structures, and a linearizing, compacting, copying scheme to reorganize all storage at the users discretion are proposed. The algorithms are designed to work well in systems which use multiple levels of storage, and large virtual address space. They depend on the fact that most cells are referenced exactly once, and that reference counts need only be accurate when storage is about to be reclaimed. A transaction file stores changes to reference counts, and a multiple reference table stores the count for items which are referenced more than once.