Virtex-II Pro FPGA Research Articles

A Secure Content Delivery System Based on a Partially Reconfigurable FPGA

We developed a content delivery system using a partially reconfigurable FPGA to securely distribute digital content on the Internet. With partial reconfigurability of a Xilinx Virtex-II Pro FPGA, the system provides an innovative single-chip solution for protecting digital content. In the system, a partial circuit must be downloaded from a server to the client terminal to play content. Content will be played only when the downloaded circuit is correctly combined (= interlocked) with the circuit built in the terminal. Since each circuit has a unique I/O configuration, the downloaded circuit interlocks with the corresponding built-in circuit designed for a particular terminal. Thus, the interface of the circuit itself provides a novel authentication mechanism. This paper describes the detailed architecture of the system and clarify the feasibility and effectiveness of the system. In addition, we discuss a fail-safe mechanism and future work necessary for the practical application of the system.

Fast Chirplet Transform With FPGA-Based Implementation

This letter presents a fast chirplet transform (FCT) algorithm, a computationally efficient method, for decomposing highly convoluted signals into a linear expansion of chirplets. The FCT algorithm successively estimates the chirplet parameters in order to represent a broad range of chirplet shapes, including the broadband, narrowband, symmetric, skewed, nondispersive, or dispersive. These parameters have significant physical interpretations for radar, sonar, seismic, and ultrasonic applications. For the real-time application and embedded implementation of the FCT algorithm, an FPGA-based hardware/software co-design is developed on Xilinx Virtex-II Pro FPGA development platform. Based on the balance among the system constraints, cost, and the efficiency of estimations, the performance of different algorithm implementation schemes have been explored. The developed system-on-chip successfully exhibits robustness in the chirplet transform of experimental signals. The FCT algorithm addresses a broad range of applications including velocity measurement, target detection, deconvolution, object classification, data compression, and pattern recognition.

Self-reconfigurable secure file system for embedded Linux

With the growth of the portable electronic devices market, not only the protection of the data for the users but also the security of the designs themselves has grown significantly in importance. A solution is presented where a Linux kernel running on a PowerPC processor included in the Virtex-II Pro FPGA family is upgraded to support hardware acceleration on the ciphering tasks. In this way all the programs running on the PPC that make use of the Linux CryptoAPI can be accelerated by hardware in a transparent way without having the programmer to rewrite the applications. To provide more flexibility, the FPGA's self-reconfiguration capability can be used to reprogram any cryptographic algorithm demanded by the Linux CryptoAPI by just including a new software driver for the operating system, thus allowing the internal configuration access port (ICAP) of the FPGA to manage any cryptographic coprocessor at any time. The approach is validated on a real application using the Linux CryptoAPI: a ciphered file system that stores the system data in a secured way.

FPGA based string matching for network processing applications

String matching is a key problem in many network processing applications. Current implementations of this process using software are time consuming and cannot meet gigabit bandwidth requirements. Implementing this process in hardware improves the search time considerably and has several other advantages. This paper presents an array based hardware implementation of this time consuming process for network intrusion detection and directory lookup applications using reconfigurable hardware. These designs are coded in VHDL targeting a Xilinx Virtex-II Pro FPGA and are evaluated in terms of the speed and resource utilization.

On Hardware Implementations Of DCT and Quantization Blocks for H.264/AVC

H.264/AVC also known as MPEG 4 part 10 or JVT, is a recently established video coding standard by the Joint Video Team (JVT) of the ISO/IEC MPEG and ITU-T VCEG. The main goal of the paper is to give a broader understanding of the design considerations for the transform and quantization blocks from H.264/AVC, by presenting area and speed optimized implementations of these blocks. The area optimized design can be used in low performance applications like mobile devices, while the speed optimized designs can be used in high definition encoders. Various designs with these blocks were synthesized with 0.18 μm TSCM technology and were also implemented on a Xilinx FPGA. The resulting gate counts were anywhere from 294 to 47,762 gates and the throughput was anywhere from 6 to 2,552 M pixels/s depending on block and optimization. In addition, a system on a programmable chip implementation of the DCT and quantization blocks is presented, which uses the Xilinx Virtex II-Pro's FPGA and its Power PC. Using this system it is possible to process 0.8 M pixels/s.

A High-End Real-Time Digital Film Processing Reconfigurable Platform

Digital film processing is characterized by a resolution of at least 2 K (2048 × 1536 pixels per frame at 30 bit/pixel and 24 pictures/s, data rate of 2.2 Gbit/s); higher resolutions of 4 K (8.8 Gbit/s) and even 8 K (35.2Gbit/s) are on their way. Real-time processing at this data rate is beyond the scope of today's standard and DSP processors, and ASICs are not economically viable due to the small market volume. Therefore, an FPGA-based approach was followed in the FlexFilm project. Different applications are supported on a single hardware platform by using different FPGA configurations. The multiboard, multi-FPGA hardware/software architecture, is based on Xilinx Virtex-II Pro FPGAs which contain the reconfigurable image stream processing data path, large SDRAM memories for multiple frame storage, and a PCI-Express communication backbone network. The FPGA-embedded CPU is used for control and less computation intensive tasks. This paper will focus on three key aspects: (a) the used design methodology which combines macro component configuration and macrolevel floorplaning with weak programmability using distributed microcoding, (b) the global communication framework with communication scheduling, and (c) the configurable multistream scheduling SDRAM controller with QoS support by access prioritization and traffic shaping. As an example, a complex noise reduction algorithm including a 2.5-dimension discrete wavelet transformation (DWT) and a full 16 × 16 motion estimation (ME) at 24 fps, requiring a total of 203 Gops/s net computing performance and a total of 28 Gbit/s DDR-SDRAM frame memory bandwidth, will be shown.

Hybrid Fault Detection Technique: A Case Study on Virtex-II Pro's PowerPC 405

Hardening processor-based systems against transient faults requires new techniques able to combine high fault detection capabilities with the usual design requirements, e.g., reduced design-time, low area overhead, reduced (or null) accessibility to processor internal hardware. This paper proposes the adoption of a hybrid approach, which combines ideas from previous techniques based on software transformations with the introduction of an Infrastructure IP with reduced memory and performance overheads, to harden system based on the PowerPC 405 core available in Virtex-II Pro FPGAs. The proposed approach targets faults affecting the memory elements storing both the code and the data, independently of their location (inside or outside the processor). Extensive experimental results including comparisons with previous approaches are reported, which allow practically evaluating the characteristics of the method in terms of fault detection capabilities and area, memory and performance overheads

The Application of Virtex-II Pro FPGA in High-Speed Image Processing Technology of Robot Vision Sensor

The Virtex-II Pro FPGA is applied to the vision sensor tracking system of IRB2400 robot. The hardware platform, which undertakes the task of improving SNR and compressing data, is constructed by using the high-speed image processing of FPGA. The lower level image-processing algorithm is realized by combining the FPGA frame and the embedded CPU. The velocity of image processing is accelerated due to the introduction of FPGA and CPU. The usage of the embedded CPU makes it easily to realize the logic design of interface. Some key techniques are presented in the text, such as read-write process, template matching, convolution, and some modules are simulated too. In the end, the compare among the modules using this design, using the PC computer and using the DSP, is carried out. Because the high-speed image processing system core is a chip of FPGA, the function of which can renew conveniently, therefore, to a degree, the measure system is intelligent.

An FPGA- Based General-Purpose Data Acquisition Controller

System development in advanced FPGAs allows considerable flexibility, both during development and in production use. A mixed firmware/software solution allows the developer to choose what shall be done in firmware or software, and to make that decision late in the process. However, this flexibility comes at the cost of increased complexity. We have designed a modular development framework to help to overcome these issues of increased complexity. This framework comprises a generic controller that can be adapted for different systems by simply changing the software or firmware parts. The controller can use both soft and hard processors, with or without an RTOS, based on the demands of the system to be developed. The resulting system uses the Internet for both control and data acquisition. In our studies we developed the embedded system in a Xilinx Virtex-II Pro FPGA, where we used both PowerPC and MicroBlaze cores, http, Java, and LabView for control and communication, together with the MicroC/OS-II and OSE operating systems