Virtex-II Field Programmable Gate Array Research Articles

An Optimization on the Neuronal Networks Based on the ADEX Biological Model in Terms of LUT-State Behaviors: Digital Design and Realization on FPGA Platforms.

Simple SummaryThe brain is an incredibly complex system possessing outstanding abilities to perform difficult tasks through a vast number of densely interconnected neurons. Aimed at discovering the underlying mechanisms of the brain, a number of spiking neural networks have been proposed to mimic biological neural dynamics. Subsequently, to perceive how the neural networks in the brain work, simulation and hardware realization of large-scale systems, similar to the brain, is an essential requirement. Behavior of a single neuron can be described by the mathematical equations in different levels of computing and biological accuracy. In this approach, a new modified ADEX model is presented based on sampling frequency by the nonlinear functions of the original model. This new model is capable for reproducing all aspects of the original model in low-error and high-degree of similarity conditions. Finally, the proposed model can be implemented on digital hardware platforms to have a real digital system. Digital results show the increase in system speed (frequency) and overall saving in hardware resources (compared by the original model and other similar works). This low-cost digital hardware is applied in large-scale neuronal networks.Design and implementation of biological neural networks is a vital research field in the neuromorphic engineering. This paper presents LUT-based modeling of the Adaptive Exponential integrate-and-fire (ADEX) model using Nyquist frequency method. In this approach, a continuous term is converted to a discrete term by sampling factor. This new modeling is called N-LUT-ADEX (Nyquist-Look Up Table-ADEX) and is based on accurate sampling of the original ADEX model. Since in this modeling, the high-accuracy matching is achieved, it can exactly reproduce the spiking patterns, which have the same behaviors of the original neuron model. To confirm the N-LUT-ADEX neuron, the proposed model is realized on Virtex-II Field-Programmable Gate Array (FPGA) board for validating the final hardware. Hardware implementation results show the high degree of similarity between the proposed and original models. Furthermore, low-cost and high-speed attributes of our proposed neuron model will be validated. Indeed, the proposed model is capable of reproducing the spiking patterns in terms of low overhead costs and higher frequencies in comparison with the original one. The properties of the proposed model cause can make it a suitable choice for neuromorphic network implementations with reduced-cost attributes.

Insight Into a Generic Interconnect Resource Model for Xilinx Virtex and Spartan Series FPGAs

With increasing scale of field-programmable gate arrays (FPGAs), the architecture of interconnect resources (IRs) in FPGAs is becoming more and more complicated. FPGAs become more vulnerable to defects during manufacturing or lifetime operation. IR testing plays an important role to guarantee correct functionality of FPGAs. This brief provides insight into a generic IR model that we developed. This IR model is a directed and weighted graph and can exhibit connection relationships among wire segments in FPGAs. Based on the generic IR model, a routing algorithm to automatically derive the minimal or near-minimal set of test configurations for IRs of Virtex and Spartan series FPGAs is also proposed. The generic IR model and associated routing algorithm are verified in Virtex, Virtex-II, Virtex-4, Virtex-5, Virtex-6, 7 Series, and Spartan series FPGAs, respectively. The experimental results demonstrate that the proposed IR model with the accompanying routing algorithm is applicable to these FPGAs with IR full coverage achieved.

Configurable Multimode Embedded Floating-Point Units for FPGAs

Performance of field-programmable gate arrays (FPGAs) used for floating-point applications is poor due to the complexity of floating-point arithmetic. Implementing floating-point units (FPUs) on FPGAs consume a large amount of resources. This makes FPGAs less attractive for use in floating-point intensive applications. Therefore, there is a need for embedded FPUs in FPGAs. However, if unutilized, embedded FPUs waste space on the FPGA die. To overcome this issue, we propose a flexible multimode embedded FPU for FPGAs that can be configured to perform a wide range of operations. The floating-point adder and multiplier in our embedded FPU can each be configured to perform one double-precision operation or two single-precision operations in parallel. To increase flexibility further, access to the large integer multiplier, adder and shifters in the FPU is provided. Benchmark circuits were implemented on both a standard Xilinx Virtex-II FPGA and on our FPGA with embedded FPU blocks. The results using our embedded FPUs showed a mean area improvement of 5.5 times and a mean delay improvement of 5.8 times for the double-precision benchmarks, and a mean area improvement of 3.8 times and a mean delay improvement of 4.2 times for the single-precision benchmarks. The embedded FPUs were also shown to provide significant area and delay benefits for fixed-point and integer circuits.

Low power field programmable gate array implementation of fast digital signal processing algorithms: characterisation and manipulation of data locality

Dynamic power consumption is very dependent on interconnect, so clever mapping of digital signal processing algorithms to parallelised realisations with data locality is vital. This is a particular problem for fast algorithm implementations where typically, designers will have sacrificed circuit structure for efficiency in software implementation. This study outlines an approach for reducing the dynamic power consumption of a class of fast algorithms by minimising the index space separation; this allows the generation of field programmable gate array (FPGA) implementations with reduced power consumption. It is shown how a 50% reduction in relative index space separation results in a measured power gain of 36 and 37% over a Cooley–Tukey Fast Fourier Transform (FFT)-based solution for both actual power measurements for a Xilinx Virtex-II FPGA implementation and circuit measurements for a Xilinx Virtex-5 implementation. The authors show the generality of the approach by applying it to a number of other fast algorithms namely the discrete cosine, the discrete Hartley and the Walsh–Hadamard transforms.

FPGA-based implementation of intelligent predictor for global solar irradiation, Part I: Theory and simulation

Recent advances in artificial intelligent techniques embedded into a Field Programmable Gate Array (FPGA) allowed the application of such technologies in real engineering problems (robotic, image and signal processing, control, power electronics, etc.), however, the application of such technologies in the solar energy field is very limited. The embedded intelligent algorithm into FPGA can play a very important role in energy and renewable energy systems for control, monitoring, supervision, etc. In this paper, the software as well as the implementation of intelligent predictors for solar irradiation on reconfigurable FPGA is described. FPGA technology was employed due to its development, flexibility and low cost. An experimental dataset of air temperature, solar irradiation, relative humidity and sunshine duration in a specific area is used; this database has been collected from 1998 to 2002 at Al-Madinah (Saudi Arabia). Initially, a MultiLayer Perceptron (MLP) is trained by using a set of 1460 patterns and then a set of 365 patterns are used for testing and validating the MLP-predictor. Six MLP-predictors (configurations) are proposed and developed by varying the MLP inputs data, while the output is always the global solar irradiation for different configurations [ G = f ˜ ( t , T , S , RH ) , G = f ˜ ( t , T , S ) , G = f ˜ ( t , T , RH ) , G = f ˜ ( t , S , RH ) G = f ˜ ( t , T ) and G = f ˜ ( t , S ) ] . Subsequently, the different MLP-predictors developed are written and simulated under the Very High Speed Integrated Circuit Hardware Description Language (VHDL) and ModelSim®. The best designed architecture for different MLP-predictors is then implemented under the Xilinx® Virtex-II FPGA (XC2v1000). The developed hardware devices permit the prediction of global solar irradiation using available air temperature, relative humidity and sunshine duration; therefore, the designed configurations are very suitable especially in areas, where there are no instruments for measuring the solar irradiation data.

Improving the Performance of Hyperspectral Image and Signal Processing Algorithms Using Parallel, Distributed and Specialized Hardware-Based Systems

Advances in sensor technology are revolutionizing the way remotely sensed data is collected, managed and analyzed. The incorporation of latest-generation sensors to airborne and satellite platforms is currently producing a nearly continual stream of high-dimensional data, and this explosion in the amount of collected information has rapidly created new processing challenges. For instance, hyperspectral signal processing is a new technique in remote sensing that generates hundreds of spectral bands at different wavelength channels for the same area on the surface of the Earth. Many current and future applications of remote sensing in Earth science, space science, and soon in exploration science will require (near) real-time processing capabilities. In recent years, several efforts have been directed towards the incorporation of high-performance computing (HPC) systems and architectures in remote sensing missions. With the aim of providing an overview of current and new trends in parallel and distributed systems for remote sensing applications, this paper explores three HPC-based paradigms for efficient implementation of the Pixel Purity Index (PPI) algorithm, available from the popular Kodak's Research Systems ENVI software package, as a representative case study for demonstration purposes. Several different parallel programming techniques are used to improve the performance of the PPI on a variety of parallel platforms, including a set of message passing interface (MPI)-based implementations on a massively parallel Beowulf cluster at NASA's Goddard Space Flight Center in Maryland and on a variety of heterogeneous networks of workstations at University of Maryland; a Handel-C implementation of the algorithm on a Virtex-II field programmable gate array (FPGA); and a compute unified device architecture (CUDA)-based implementation on graphical processing units (GPUs) of NVidia. Combined, these parts deliver an excellent snapshot of the state-of-the-art in those areas, and offer a thoughtful perspective on the potential and emerging challenges of adapting HPC systems to remote sensing problems.

Clusters Versus FPGA for Parallel Processing of Hyperspectral Imagery

Hyperspectral imaging is a new technique in remote sensing that generates images with hundreds of spectral bands, at different wavelength channels, for the same area on the surface of the Earth. Although in recent years several efforts have been directed toward the incorporation of parallel and distributed computing in hyperspectral image analysis, there are no standardized architectures for this purpose in remote sensing missions. To address this issue, this paper develops two highly innovative implementations of a standard hyperspectral data processing chain utilized, among others, in commercial software tools such as Kodak's Research Systems ENVI software package (one of the most popular tools currently available for processing remotely sensed data). It should be noted that the full hyperspectral processing chain has never been implemented in parallel in the past. Analytical and experimental results are presented in the context of a real application, using hyperspectral data collected by NASA's Jet Propulsion Laboratory over the World Trade Center area in New York City, shortly after the terrorist attacks of September 11th 2001. The parallel implementations are tested in two different platforms, including Thunderhead, a massively parallel Beowulf cluster at NASA's Goddard Space Flight Center, and a Xilinx Virtex-II field programmable gate array (FPGA) device. Combined, these platforms deliver an excellent snapshot of the state-of-the-art in those areas, and offer a thoughtful perspective on the potential and emerging challenges of incorporating parallel processing systems into realistic hyperspectral imaging problems.

Higher Radix and Redundancy Factor for Floating Point SRT Division

The execution performances of the Sweeney, Robertson, Tocher (SRT) division algorithm depend on two parameters: the radix-r and the redundancy factor p. In this paper, a study of the effect of these parameters on the division performances is presented. At each iteration, the SRT algorithm performs a multiplication by the quotient digit qi+1. This last can be just a simple shift, if the digit qi i +1is a power of two (qi+1 = 2k), otherwise, the SRT iteration needs a multiplier. We propose, in this work, an approach to circumvent this multiplication by decomposing the quotient digit qi+1 into two or three terms multiples of 2. Then, the multiplication is carried out by simple shifts and a carry save addition. The implementation of this approach on Virtex-II field-programmable gate-array (FPGA) circuits gives best performances than the approach which uses the embedded multipliers 18times18 bits. The iterations delays are operands sizes independent. The reduction tree delays are at most equivalent to the delay of two Virtex-II slices. This approach was tested for the 4, 8, and 16 radixes in the two cases of minimum and maximum redundancy factors. By this study, we conclude that the use of the radix-8 with a maximum redundancy factor gives the best performances by using our approach for the double precision computation of the SRT division.

FPGA Dynamic Power Minimization through Placement and Routing Constraints

Field-programmable gate arrays (FPGAs) are pervasive in embedded systems requiring low-power utilization. A novel power optimization methodology for reducing the dynamic power consumed by the routing of FPGA circuits by modifying the constraints applied to existing commercial tool sets is presented. The power optimization techniques influence commercial FPGA Place and Route (PAR) tools by translating power goals into standard throughput and placement-based constraints. The Low-Power Intelligent Tool Environment (LITE) is presented, which was developed to support the experimentation of power models and power optimization algorithms. The generated constraints seek to implement one of four power optimization approaches: slack minimization, clock tree paring, N-terminal net colocation, and area minimization. In an experimental study, we optimize dynamic power of circuitsmapped into 0.12 µm Xilinx Virtex-II FPGAs. Results show that several optimization algorithms can be combined on a single design, and power is reduced by up to 19.4%, with an average power savings of 10.2%.

Dynamic testing of Xilinx Virtex-II field programmable gate array (FPGA) input/output blocks (IOBs)

Heavy-ion irradiation and fault injection experiments were conducted to evaluate the upset sensitivity of the Xilinx Virtex-II field programmable gate arrays (FPGAs) input/output block (IOB). Full triple module redundancy (TMR) of the IOBs, in combination with regular configuration scrubbing, proved to be a quite effective upset mitigation method.

Comparison of Xilinx Virtex-II FPGA SEE sensitivities to protons and heavy ions

A comparison of heavy-ion and proton-induced single event effect sensitivities has been made using the Xilinx Virtex-II field programmable gate array (FPGA). Recently fabricated test samples are selected for observations of single event upset and single event functional interrupt. A complex relationship appears to exist between the heavy ion and proton sensitivities due to effects such as multiple-bit upsets and elastic nuclear scattering.