VHDL Code Research Articles

Low power RTL implementation of Tiny-YOLO-v2 DCNN hardware accelerator on Virtex-7 FPGA

Deep Convolution Neural Networks (DCNNs) are widely used in real-time applications, including image classification, speech recognition, and object detection. However, there are challenges for real-time applications on portable devices like mobile phones or embedded systems. Most object detection models are optimized for desktop configurations, requiring fast GPUs. Shallower networks with fewer computational complexities have been proposed for real-time detection, but ultimately compromise detection accuracy. Performance and complexity trade-offs are significant for computationally complex deep networks. This work aims to implement the CNN-based object detection model Tiny-Yolo-v2 on a Field Programmable Gate Array (FPGA) using Register Transfer Logic (RTL) as a native language. Hardware implementation is synthesized on The AMD Virtex 7 FPGA VC709 Connectivity Kit using VHDL code on Vivado 2020.1. This is the first, up to the authors' knowledge, RTL implementation of the Tiny-Yolo-v2 object identification algorithm on FPGA. The power consumed by the CNN layers equals 7.09W at a frequency of 100MHz.

Rapid Prototyping and Hardware-In-the-Loop Verification of Enhanced Sliding Mode Control of an Asynchronous Machine Using a Xilinx System Generator and an FPGA-Zynq Board

This article describes rapid prototyping using the Xilinx system generator (XSG) of a direct field oriented control (DFOC) strategy based on improved super twisting sliding mode controllers (ISTSMCs) of an asynchronous machine to succeed a hardware implementation on a field programmable gate array (FPGA) board. The main goal is to enhance regulation loops governing rotor speed, rotor flux, and stator current components within the classical DFOC structure. These ISTSMCs replace integral proportional controllers, resulting in improved system dynamics, faster speed and torque responses, and heightened robustness against load and rotor resistance variations, surpassing other control methods. Additionally, the article aims to implement this DFOC-ISTSMC method on an FPGA board to reduce control system sampling time and loop delays, leveraging the FPGA’s parallel processing capabilities. The hardware architecture is designed using XSG in the MATLAB/Simulink environment, enabling effective simulation, testing, discrete algorithm creation, and VHDL code generation for FPGA implementation via the hardware-in-the-loop (HIL) process. Assessment involves digital simulation studies and HIL processes using XSG with a Xilinx FPGA Zynq 7000 under MATLAB/Simulink, demonstrating improved system performance, reduced time delays, and efficient FPGA utilization. This approach validates the effectiveness of the proposed DFOC-ISTSMC algorithm in enhancing control strategy for asynchronous machines.

Accelerating autonomous vehicles: Harnessing FPGA power for deep learning advancements

In the rapidly developing field of autonomous vehicles (AV), the integration of deep learning algorithms has become the cornerstone for improving vehicle perception and decision-making ability. This study investigates the potential of field-programmable gate arrays (FPGAs) as hardware accelerators for deep-learning tasks in self-driving cars. This study used a Zynq UltraScale+ MPSoC FPGA board from Xilinx, known for its performance and adaptability, and combined it with a high-resolution camera to simulate real-world visual data encountered by AVs. The approach involved implementing a convolutional neural network (CNN) to perform tasks such as object detection, lane detection, and traffic sign classification. The model was quantized and converted to VHDL code using Xilinx Vivado HLS to optimize the deep learning algorithm for FPGA.The results show that the FPGA-based model significantly outperforms the traditional CPU-based model in terms of processing speed and energy efficiency without sacrificing accuracy. This study highlights the critical role of FPGAs in supporting deep learning tasks in self-driving cars and paves the way for safer and more efficient transportation solutions in the future.

Insulation Detection of Electric Vehicles by Using FPGA-Based Recursive-Least-Squares Algorithm

The principal reason for why electric vehicles are required to serve as an alternative to the more widespread gasoline and petroleum-based vehicles used in modern times is due to the use of an environmentally conscious means of transportation or to circumvent the tumultuous economic dealings of the compressed natural gas and petroleum industries. There is a growing daily need for large, high-voltage e-mobilities, mostly driven by anticipated advancements in electric vehicle technology. Consequently, all of the various components of these vehicles must be able to be accommodated within a limited and compact space. The battery is an essential component in e-mobility. The insulation, health monitoring, and problem diagnostics of lithium-ion (Li-ion) batteries are of utmost importance in ensuring these vehicles’ safety and efficient functioning. Real-time and fast insulation detection techniques are required to ensure safety in high-voltage (HV) vehicles and to avoid insulation failure. This paper used the Recursive-Least-Squares (RLS) algorithm because it is computationally efficient for building the insulation detection system. Based on the RLS technique, we proposed field programmable gate array (FPGA)-based algorithms and implemented them using VHDL coding. The FPGA is very fast at detection, and the error is lower. We validated the FPGA results with MATLAB simulation results from the existing literature, and the errors are much less when using FPGAs. An experimental hardware platform was also created to validate the proposed FPGA technique with various motor and resistive loadings on electric vehicles (EVs).

Fault Identification in Modified Hybrid Digital Pulse Width Modulation using Triple Modular Redundancy

In this paper, the fault analysis is performed for the identification in the Modified Hybrid Digital Pulse Width Modulation by making use of the Triple Modular Redundancy method. The developed algorithm is real time implemented using the Xilinx Artix 7 FPGA device. The Modified Hybrid Digital Pulse Width Modulation is designed for the purpose of minimizing the Turn-ON and Turn-OFF delays in the triggering event of the generated Digital Pulse Width Modulation. Though additional compensatory circuits are added for the delay reduction, the area utilization is still low when implemented in FPGA device. Also, the Triple Modular Redundancy consists of three times of MHDPWM signal generation to check for the fault occurrence. For the sake of validating the fault identification, the majority voter circuit is used that could find the error at the earliest. The proposed method is checked for errors by inducing within the VHDL code and trailed with multiple duty cycle values. The proposed fault identification method is validated for VLSI parameters such as area, delay and power.

FPGA based modified multi-repeat distribution matcher for probabilistic amplitude shaping

The technique of probabilistic amplitude modulation, based on distribution matching, has garnered considerable attention in recent years as a means to enhance spectral efficiency and diminish the constellation energy of coded modulation. This paper introduces the implementation of Probabilistic Amplitude Modulation (PAS) using a Modified Multi-Repeat Distribution Matcher (MMRDM) on a Field Programmable Gate Array (FPGA). The Modified Multiple Repetition Distribution Matcher (MMRDM) is integrated into a 2×2 Multiple Input Multiple Output Orthogonal Frequency Division Multiplexing (MIMO-OFDM) system, realized through the Xilinx System Generator (XSG). Simple Zero-Forced and Minimum Mean Squared Error (MMSE) equalizers are applied to the receiver for signal detection across the MIMO channel. The system incorporates enhanced security through chaos-based scrambling with 16 and 64 Quadrature Amplitude Modulation (QAM). VHDL code files for this system are generated for the Xilinx Kintex-7 (xc7k325t-3fbg676) for hardware implementation. Performance evaluation includes an assessment of required storage capacity, complexity, and bit error rate (BER). Using Vivado 2017.4, the system is successfully routed with resource utilization, for example, 0.67% Block RAM (BRAM), 68.6% Look-Up Tables (LUT), 83% DSP 48s, and 1.5% registers for 64-QAM uniform modulation. Similarly, for 64-QAM 10 level (shaper output 60 bit) shaped modulation, the resource utilization is 0.67% BRAM, 68.8% LUT, 83% DSP 48s, and 1.6% registers on the specified device. Simulation results demonstrate an improvement in the net shaping gain of approximately (2-4 dB) at 1×10^(-4) for different equalizer cases compared to uniform QAM, along with a notable reduction in required storage capacity and computational complexity.

Performance Comparison of 7-level Multi-Level Inverter Topologies using FPGA

This paper compares the Multi-Level Inverter namely Switched Ladder and H-Bridge Topologies for the performance parameters. The topologies considered are fed with the switch patterns from the non-carrier angle manipulated formula. The switching angle algorithm identifies on which particular angle the signal has to be generated. It is identified based on four algorithm namely half height method, equal phase method,This paper concentrates on the 7-level MLI AC output using the synthesizable VHDL code and implemented using the FPGA in real-time. For verification in simulation, the cross-compiling is attained using the System Generator tool.

FPGA implementation of KNN Algorithm-Based Prediction for DPWM Methods

This paper presents the prediction of the DPWM methods using the FPGA device. For the sake of prediction, the parameters such as Clocking frequency, switching frequency, positive duty cycle value, and negative duty cycle value are considered by taking 23 samples of the real-time results obtained for the DPWM techniques. Based on the dataset, the parametric values are fed into the KKN algorithm to predict the suitable DPWM technique by identifying the K-nearest neighbor. The proposed KNN algorithm for the DPWM technique prediction is developed using the VHDL code and synthesized in the FPGA board for real-time validation. Also, the ASIC IC layout design for the proposed method is generated using the Cadence EDA tool. The performance analysis for the power, area, and delay are evaluated using the Xilinx and Cadence Tool.

Design of Multiplexers using Reversible Logic Technique

Reversible logic is promising as it can be applied to different applications in low power like nanocomputing especially in quantum computing. Reversible logic is a technioue for power reduction. Reversible circuits are similar to digital circuits but they work using reversible logic gates. This study focuses on reducing the garbage output and ancilla inputs in reversible multiplexers, thereby reducing the power consumption. In this study two designs of Multiplexers are given. Design1 is using TwinSJ gate and AJ gate. 2:1, 4:1 and 8:1 multiplexers are built. In Design 2, a new gate (SJ gate) is built which functions as 2:1 multiplexer. It has 4*4 configuration. The inputs are suitably configured so that it performs various logic functions. Using this SJ gate and other basic reversible logic gates, 2:1, 4:1 and 8:1 multiplexers are built. In 2:1 multiplexer, Ancilla inputs are improved to '0' from 5 and garbage output has been reduced to 2 against 7 in existing design. 4:1 multiplexers are built with ‘0’ ancilla inputs against 2 and 11 in existing designs. Garbage output of the proposed 4:1 multiplexer is 5 against 6 and 16 in existing designs. 8:1 multiplexer is built with 1 ancilla input and 11 garbage output against 2 and 12 respectively in existing design. This is designed using VHDL code - xilinx 14.7 for verification purpose and simulated on ISIM.

FPGA realization of four chaotic interference cases in a terrestrial trajectory model and application in image transmission

This article presents a technique to integrate two dynamical models, a four-wing spherical chaotic oscillator and the elliptical path described by the planet Earth during its translation movement around the sun. Four application cases are derived from the system by varying the dynamics of the chaotic oscillator and these can be applied in information encryption to transmit RGB and grayscale images modulated by CSK. Consequently, the three main contributions of this work are (1) the emulation of the trajectories of the planet Earth with chaotic interference, (2) the CSK modulation and image encryption in a master-slave synchronization topology, and (3) the CSK demodulation for decryption without loss of information with respect to the original information. The three contributions are based on VHDL code implementation. The results of the synchronization, encryption and decryption technique were verified by means of time series and the encrypted images showed a correlation less than − 0.000142 and − 0.0003439 for RGB and grayscale format, respectively, while the retrieved image shows a complete correlation with the image original. In this work, the co-simulations were performed between MATLAB/Simulink and Vivado, using the VHDL language on two FPGA boards from different manufacturers, namely, Xilinx Artix-7 AC701 and Intel Cyclone IV.

Classification of Emotion using Eeg Signals: an FPGA Based Implementation

An electroencephalograph is a device that records all electrical energy in the human brain using wearable metal electrodes placed on the skull. Electrical impulses connect brain cells and are always mobile, even at rest. This activity appears as a squiggly line in EEG recordings. Activity gaze data is pre-processed to a frequency range of 0 to 75 Hz. This creates a new matrix with a sample rate of 200 Hz and a range of 0-75 Hz. A finite-impulse-response low-pass filter was used because the bandpass would distort his EEG data after processing. Each pre-processed EEG signal has an output, which completes feature extraction. Principal Component Analysis or PCA is passed in the feature reduction phase. PCA is an analytical process that uses singular value decomposition to transform a collection of corresponding features into mutually uncorrelated features or principal components. Principal component analysis: (a) mean normalization of features (b) covariance matrix (c) eigenvectors (d) reduced features or principal components. The above steps are passed to the SVM classifier for sentiment output. His VHDL code and testbench for 2*2 matrices were written, waveforms and RTL schemes were created in Xilinx 14.5. For the FPGA implementation, a Simulink model was designed, and the eigenvalues were pre-determined using a system generator.

Design and Implementation of a Multiplier free FPGA based OFDM Transmitter

Orthogonal Frequency Division Multiplexing (OFDM) is an efficient multi-carrier technique.The core operation in the OFDM systems is the FFT/IFFT unit that requires a large amount of hardware resources and processing delay. The developments in implementation techniques likes Field Programmable Gate Array (FPGA) technologies have made OFDM a feasible option. The goal of this paper is to design and implement an OFDM transmitter based on Altera FPGA using Quartus software. The proposed transmitter is carried out to simplify the Fourier transform calculation by using decoder instead of multipliers. After programming ALTERA DE2 FPGA kit with implemented project, several practical tests have been done starting from monitoring all the results of the implemented blocks (VHDL code) and compare them with corresponding results from simulation system implemented in matlab 2010a. The results of these practical tests show that the suggested approach gives a significant improvement in reducing complexity and processing delays (45 nsec) in comparison with the conventional implementations of OFDM transmitter.

Mathematical Modeling and Analysis of Capacitor Voltage Balancing for Power Converters with Fewer Switches

The multilevel inverter (MLI) has been developed as a powerful power conversion scheme for several processes, including renewable energy, transmission systems, and electric drives. It has become popular across medium- to high-power operations due to its many advantages, including minimum harmonic content, low switching losses, and reduced electromagnetic interference (EMI). In this paper, the capacitor voltage balancing technique-based pulse width modulation (PWM) has been proposed. The proposed PWM strategy offers several advantages, such as high-quality output waveforms with reduced harmonic distortion, improved efficiency, and better control over the output voltage. The Xilinx ISE 10.1 software was used for synthesizing, and the VHDL code was written for the proposed method. MATLAB software was used to simulate and hardware was used to verify the proposed system. The SPARTAN 3E FPGA was used for the generation of the PWM. This paper developed a 2 kW single-phase 15-level inverter that created an AC wave from the DC input voltage, with a total harmonic distortion (THD) of 8.02%, which was less than the THD achieved from other conventional MLI. The results indicate that MLI topologies with low total harmonic currents, fewer switches, and higher output voltage levels are better stabilized during load disturbance circumstances.

Implementation of Traffic Light Controlling System for a Simple Intersection with VHDL using Quartus II

In the era of urbanization in the 21st century, the number of vehicles on the road has increased drastically to cope with the increased population of the city which directly affects the traffic on the street and more importantly on intersections. Automatic traffic signaling system can plays a vital role to mitigate vehicle congestion in the critical intersections of the busy roads. To ensure hassle free mobility of vehicles in the intersection on the street, the appropriate traffic signal lights are necessary that coordinate traffic in various directions on the streets. A simple intersection on the road is considered for the simulation of traffic signaling system. VHDL code was written in Quartus II to implement traffic light system for specific intersections on the road. The vehicles are always moving on the main road, meaning green light is always ‘1’ until there are vehicles approaching the side road. When the vehicles arrive on the side road which is sensed by sensor, then the traffic controller takes the initiative to schedule the traffic light, from green to red light in the main road and red to green light in the side road. The proposed traffic signaling system works properly, which is verified during simulation. In this paper, simple intersection is considered due to simple design and easy implementation.

Fuzzy Hardware Tool: An Adaptable Tool to Facilitate the Implementation of Fuzzy Inference Systems in Hardware

A Fuzzy Inference System (FIS) is a system that represents human reasoning based on fuzzy if-then rules to extract valid results from imprecise or uncertain information. These systems have been applied to various engineering fields, such as control and image recognition, and have encouraged the search for development tools that provide facilities for the design, simulation, and implementation of FISs. Most of the available software tools for the design of FISs have been developed by the scientific community, and very few are commercial tools. According to the state of the technology, the fuzzy systems implemented in hardware have shown higher performance than software implementations. For this reason, different strategies for automatic hardware synthesis of FISs have been proposed in the literature. The available tools for FIS implementation, including MATLAB, Simulink, and Xfuzzy environment, require advanced hardware knowledge, and it is necessary to synthesize and implement the program on FPGA each time a change is made to the code. This paper presents a novel approach for the implementation of fuzzy systems on hardware devices that enables the direct implementation of FISs through a graphical user interface. The VHDL code is pre-synthesized and integrated with the interface, allowing users to experiment with different input parameters, such as membership functions and fuzzy rules, without resynthesizing the code on an FPGA. To verify the effectiveness of the proposed approach, experiments were conducted on two similar System-on-Chip (SoC) devices, VEEK-MT and VEEK-MT2. The results showed that the proposed solution represents a significant advancement in the study of fuzzy systems on hardware devices, providing a flexible and user-friendly approach to their design and implementation.

Efficient Modulo Multiplier

The paper presents the methodology to compute modulo multiplication with the moduli set 2n, 2n−1, 2n+1. In addition to this, designs of the modulo multipliers, namely 2n, 2n−1, and 2n+1 (with n = 4, 8, and 16), have been proposed which are based on half adders, full adders, 4:3 compressor, 7:3 compressor, and the multi-column compressor namely 5,5:4. The gate level design of 4:3 compressor is carried out by solving the truth table using the K-map reduction. To verify the functionalities we have implemented the proposed modulo multipliers using VHDL coding in Xilinx 14.2 design suite. Simulation using Virtex-6 device has been performed to estimate delay, power consumption, and power-delay product (PDP). Moreover, the modulo multipliers are simulated in Cadence RC compiler using 0.18 µm technology to estimate the area. One of the major contributions to the arts of this work is in the partial product reduction stage which utilizes the multi-column 5,5:4 compressor to reduce power and area. The modulo 2n−1 multiplier of operand size 4-bit shows an improvement of 66.34% in terms of area over the best-reported paper. On the other hand, the modulo 2n+1 multiplier of operand size 4-bit shows an improvement of 58.59% terms of in area and the same of operand size 8-bit shows an improvement of 22.72% over the best-reported paper. The proposed algorithms of moduli multiplication are applicable to Booth multiplication of signed numbers.

Fixed-point implementations for feed-forward artificial neural networks

We present scalable and generalized fixed-point hardware designs (source VHDL code is provided) for Artificial Neural Networks (ANNs). Three architectures are presented: multiply-and-add, multiplier-less, fully pipelined. In addition, we include two approaches for ANN binary layers: accumulation-based and fully pipelined. The fully customized hardware architectures allow for design space exploration to establish trade-offs among numerical format, processing time, resource usage, and numerical accuracy. Users can select the ANN architecture, ANN parameters (structure, weights, biases), the numerical format for both the input/output data in every layer and the network parameters (weights and biases). Results are presented in terms of resources, processing time, and numerical accuracy. The proposed architectures were implemented on modern FPGAs. These hardware designs are expected to be used as building blocks on a variety of applications such as CNNs and SNNs, as well as a platform for educational purposes.

The upgraded quench protection system for main quadrupoles in the LHC

The protection of superconducting magnets is a very important issue and demanding challenge in the LHC and other superconducting accelerating facilities. The quench phenomenon can destroy components of the accelerator, and therefore this digital system was designed, implemented, tested, and installed near each superconducting magnet in the LHC tunnel. The quench detection principle relies on the extraction of resistive voltage by compensation of the inductive part of the voltage. This article presents briefly the architecture applied to the design and the validation of the FPGA-based quench detector for the main quadrupoles of the LHC. The article focusses on digital design with the use of FPGA by VHDL coding and on the verification by simulation. The design is a replacement for the old detection system.

ARASP: An ASIP Processor for Automated Reversible Logic Synthesis

Reversible logic has been emerged as a promising computing paradigm to design low power circuits in recent years. The synthesis of reversible circuits is very different from that of non-reversible circuits. Many researchers are studying methods for synthesizing reversible combinational logic. Some automated reversible logic synthesis methods use optimization algorithms Optimization algorithms are used in some automated reversible logic synthesis techniques. In these methods, the process of finding a circuit for a given function is a very time-consuming task, so it’s better to design a processor which speeds up the process of synthesis. Application specific instruction set processors (ASIP) can benefit the advantages of both custom ASIC chips and general DSP chips. In this paper, a new architecture for automatic reversible logic synthesis based on an Application Specific Instruction set Processors is presented. The essential purpose of the design was to provide the programmability with the specific necessary instructions for automated synthesis reversible. Our proposed processor that we referred to as ARASP is a 16-bit processor with a total of 47 instructions, which some specific instruction has been set for automated synthesis reversible circuits. ARASP is specialized for automated synthesis of reversible circuits using Genetic optimization algorithms. All major components of the design are comprehensively discussed within the processor core. The set of instructions is provided in the Register Transform Language completely. Afterward, the VHDL code is used to test the proposed architecture.

Comparison study of hardware architectures performance between FPGA and DSP processors for implementing digital signal processing algorithms: Application of FIR digital filter

The objective of this project is to make a detailed study on the Hardware architectures of DSP and FPGA then to carry out a comparison between the two platforms in order to achieve a better implementation while keeping to increase the performances and obtain a better signal processing quality. For this raison, we wanted to make a digital FIR filter of 40 order bandpass and a symmetrical parallel architecture of this FIR filter. Matlab's FDATOOL is used to design this filter. This tool allows us to generate the VHDL code of the filter to implement it on Altera Cyclone III FPGA which is placed on the Texas Instruments TSW6011 board, this tool also allows us to generate all the coefficients of our filter in a header file C in order to use them in a program of the FIR filter written in C which will then be loaded on the DSP TMS320C6713. This achievement allows us to distinguish between different hardware architectures and make a comparison in terms of execution speed and power consumption.