FPGA implementation of KNN Algorithm-Based Prediction for DPWM Methods

Abstract

This paper presents the prediction of the DPWM methods using the FPGA device. For the sake of prediction, the parameters such as Clocking frequency, switching frequency, positive duty cycle value, and negative duty cycle value are considered by taking 23 samples of the real-time results obtained for the DPWM techniques. Based on the dataset, the parametric values are fed into the KKN algorithm to predict the suitable DPWM technique by identifying the K-nearest neighbor. The proposed KNN algorithm for the DPWM technique prediction is developed using the VHDL code and synthesized in the FPGA board for real-time validation. Also, the ASIC IC layout design for the proposed method is generated using the Cadence EDA tool. The performance analysis for the power, area, and delay are evaluated using the Xilinx and Cadence Tool.