Very Large Scale Integration Devices Research Articles

A Survey on VLSI Implementation of AES Algorithm with Dynamic S-Box

In recent research, very large-scale integration (VLSI) design and its implementation plays a major role. It has been considered as compact and contains additional techniques. However, it undergoes security threats like differential power analysis (DPA) attacks, confidential information leakage, suspicious data insertion, brute force attacks, and other severe attacks. Hence, the cryptographic techniques that have been implemented to enhance the security level for VLSI devices is the focus of this survey. The symmetric cryptographic technique of advanced encryption standard (AES) is considered suitable for this security enhancement and it is an advanced encryption process, and so the intelligible data are transmitted in an unintelligible form to confuse the attackers and the data is securely transmitted without any interruption. Different techniques to implement the AES approaches in VLSI devices are analyzed. The dynamic S-box technique is also analyzed for key-dependent processes. The key-dependent S-box of block ciphers is more secure than a general fixed S-box. The strength of the cipher is increased by the usage of an S-box. A dynamic S-box, generated to be key-dependent and with a discrete logarithmic approach, enhanced the S-box nonlinearity. Several measures analyzed regarding security and complexity of nonlinear transformation of S-box improved. Hence, the AES algorithm with dynamic S-box makes the system dynamic, more nonlinear, and with an unbreakable architecture. In this review, it also identified that to implement nonlinear transformation in AES, an S-box component has been used. This survey has been provided as guidelines for VLSI architecture implementation in a more secure way with cryptographic algorithm of AES and a dynamic S-box.

Total ionizing dose effects and radiation testing of complex multifunctional VLSI devices

Total ionizing dose (TID) effects and radiation tests of complex multifunctional Very-large-scale integration (VLSI) integrated circuits (ICs) rise up some particularities as compared to conventional ?simple? ICs. The main difficulty is to organize informative and quick functional tests directly under irradiation. Functional tests approach specified for complex multifunctional VLSI devices is presented and the basic radiation test procedure is discussed in application to some typical examples.

Countermeasure against Side Channel Power Attacks in Cryptography Devices

Power attack is the most powerful side channel attacks in cryptography chip during VLSI (Very Large Scale Integration) testing. Hackers attack the target devices by means of power through finding the correlations between the power spikes for different input generated on Cathode Ray Oscilloscope (CRO). To overcome such a great issues we proposed the novel techniques for cryptography devices which perform their crypto functions without an external power source. Energy required to do the cryptographic operation is provided by Embedded Capacitance Power Supply (ECPS) method, which is integrated with the VLSI device. Group of capacitors are connected to form the power supply, which act as the temporary battery of the cryptographic chip. The power spikes for this crypto operation not visible by the CRO. Hence it is complicate for attackers to hack the crypto system. The proposed method is modelled through Hardware Description Language (HDL) Verilog-AMS using Switch Level Modelling and result is verified by simulation wave form generated.

Dynamic neural fields as a step toward cognitive neuromorphic architectures

Dynamic Field Theory (DFT) is an established framework for modeling embodied cognition. In DFT, elementary cognitive functions such as memory formation, formation of grounded representations, attentional processes, decision making, adaptation, and learning emerge from neuronal dynamics. The basic computational element of this framework is a Dynamic Neural Field (DNF). Under constraints on the time-scale of the dynamics, the DNF is computationally equivalent to a soft winner-take-all (WTA) network, which is considered one of the basic computational units in neuronal processing. Recently, it has been shown how a WTA network may be implemented in neuromorphic hardware, such as analog Very Large Scale Integration (VLSI) device. This paper leverages the relationship between DFT and soft WTA networks to systematically revise and integrate established DFT mechanisms that have previously been spread among different architectures. In addition, I also identify some novel computational and architectural mechanisms of DFT which may be implemented in neuromorphic VLSI devices using WTA networks as an intermediate computational layer. These specific mechanisms include the stabilization of working memory, the coupling of sensory systems to motor dynamics, intentionality, and autonomous learning. I further demonstrate how all these elements may be integrated into a unified architecture to generate behavior and autonomous learning.

Stress Engineering of Backend Metallization

The backend structures of advanced VLSI (Very-Large Scale Integration) devices have become increasingly complex because of the need to combine several types of dielectric and metal layers in order to enhance device performance and/or reliability. For example, the inter-metal dielectric (IMD) stack of an aluminum-metallization device may consist of high density plasma (HDP) fluorine-doped silicate glass (FSG) for gap fill and RC-delay minimization, plus a silicon-rich oxide (SRO) cap to prevent aluminum attack from fluorine out-diffusion. Depending on the interplay between the tensile stress of the aluminum, and the typically compressive stress of the dielectric stack, the wafer may develop a large bow of either positive or negative sign. A large positive bow may negatively impact wafer handling during processing steps that use vacuum chucking, and can also lead to excessive edge polishing during tungsten and oxide chemical–mechanical planarization (CMP) steps. This paper presents a methodology to reduce final wafer bow from ~+40 to ~-10 micron by a careful selection of SRO deposition conditions to achieve a stress value that results in flatter wafers.

A neuromorphic VLSI device for implementing 2D selective attention systems

Selective attention is a mechanism used to sequentially select and process salient subregions of the input space, while suppressing inputs arriving from nonsalient regions. By processing small amounts of sensory information in a serial fashion, rather than attempting to process all the sensory data in parallel, this mechanism overcomes the problem of flooding limited processing capacity systems with sensory inputs. It is found in many biological systems and can be a useful engineering tool for developing artificial systems that need to process in real-time sensory data. In this paper we present a neuromorphic hardware model of a selective attention mechanism implemented on a very large scale integration (VLSI) chip, using analog circuits. The chip makes use of a spike-based representation for receiving input signals, transmitting output signals and for shifting the selection of the attended input stimulus over time. It can be interfaced to neuromorphic sensors and actuators, for implementing multichip selective attention systems. We describe the characteristics of the circuits used in the architecture and present experimental data measured from the system.

Modeling selective attention using a neuromorphic analog VLSI device.

Attentional mechanisms are required to overcome the problem of flooding a limited processing capacity system with information. They are present in biological sensory systems and can be a useful engineering tool for artificial visual systems. In this article we present a hardware model of a selective attention mechanism implemented on a very large-scale integration (VLSI) chip, using analog neuromorphic circuits. The chip exploits a spike-based representation to receive, process, and transmit signals. It can be used as a transceiver module for building multichip neuromorphic vision systems. We describe the circuits that carry out the main processing stages of the selective attention mechanism and provide experimental data for each circuit. We demonstrate the expected behavior of the model at the system level by stimulating the chip with both artificially generated control signals and signals obtained from a saliency map, computed from an image containing several salient features.

Recent advances in plastic packaging of flip-chip and multichip modules (MCM) of microelectronics

The success in consumer electronics in the 1990's will be focused on low-cost and high performance electronics. Recent advances in polymeric materials (plastics) and integrated circuit (IC) encapsulants have made high-reliability very-large-scale integration (VLSI) plastic packaging a reality. High-performance polymeric materials possess excellent electrical and physical properties for IC protection. With their intrinsic low modulus and soft gel-like nature, silicone gels have become very effective encapsulants for larger, high input/output (I/O) (in excess of 10 000), wire-bonded and flip-chip VLSI chips. Furthermore, the recently developed silica-filled epoxies underfills, with the well controlled thermal coefficient of expansion (TCE), have enhanced the flip-chip and chip-on-board, direct chip attach (DCA) encapsulations. Recent studies indicate that adequate IC chip surface protection with high-performance silicone gels and epoxies plastic packages could replace conventional ceramic hermetic packages. This paper will review the IC technological trends, and IC encapsulation materials and processes. Special focus will be placed on the high-performance silicone and epoxy underfills, their chemistries and use as VLSI device encapsulants for single and multichip module applications.

Recent advances in hermetic equivalent flip-chip hybrid IC packaging of microelectronics

Recent advances in polymeric materials and integrated circuit (IC) encapsulants have made high-reliability very large-scale integration (VLSI) plastic packaging a reality. High-performance silicone gel possesses excellent electrical and physical properties for IC protection. With their intrinsic low modulus and soft gel-like nature, silicone gels have become very effective encapsulants for larger, high I/O, wire-bonded and flip-chip VLSI chips. Furthermore, the recently developed silica-filler modified epoxies, with the well-controlled thermal coefficient of expansion (TCE), have enhanced the flip-chip and chip-on-board hybrid IC encapsulation. Recent studies indicate that, with adequate IC chip surface protection with high-performance silicone gels and epoxies, plastic packages could replace conventional ceramic hermetic packages. This paper reviews the IC technological trends, and IC encapsulation materials and processes. Special focus is placed on the high-performance silicone gel, epoxies and polyimides, their chemistry and use as VLSI device encapsulants for single and multi-chip module applications.

VLSI in biomedical imaging systems

This paper explores the nature of Very Large Scale Integration (VLSI) systems as applied to the area of medical imaging systems. A general discussion of imaging systems and the techniques employed therein will be presented. With this, the merits of VLSI solutions to the medical imaging problem are presented. Consideration is also given to programmable processors, such as off the shelf DSP processors, semi-custom, and full custom VLSI devices. Through the use of VLSI devices, many image processing algorithms can be integrated into a hardware solution. This has the advantage of increased computational capacity over solutions that would normally employ software techniques.

Low Dielectric Constant Interlayer Using Fluorine-Doped Silicon Oxide

A new interlayer dielectric film using fluorine-doped silicon oxide (SiOF) for multilevel interconnection of very large scale integration (VLSI) has been fabricated. The film is deposited by a simple technique, which is hexafluoroethane ( C2F6) addition to conventional tetraethoxysilane (TEOS)-based plasma-enhanced chemical vapor deposition (PE-CVD). Si–F bond formation in the film is detected by chemical bonding structural studies using Fourier transform infrared spectroscopy (FT-IR) and X-ray photoelectron spectroscopy (XPS). Low dielectric constants caused by Si–F bond formation and good gap-filling ability due to in situ etching by C2F6 plasma are obtained. Therefore, SiOF film has very high applicability as an interlayer dielectric film for advanced VLSI devices.

Amorphous oxide precipitates in silicon single crystals

Czochralski-grown dislocation-free silicon single crystals1 are used almost exclusively by the semiconductor industry in the manufacture of contemporary VLSI (very large-scale integration) devices. These crystals contain small concentrations of dissolved oxygen, which diffuses on heating to form precipitates of silica. Because VLSI device performance depends on the size and distribution of such precipitates the characterization of these precipitates is of immense current technological interest. The volume fraction of the precipitates is only of the order of 10 parts per million, which makes their characterization extremely difficult. Here we show that the technique of small-angle neutron scattering can be used to fully characterize, in a single experiment, the precipitates (in terms of orientation, size, number density and volume fraction) in sample volumes of ∼10 cm3. This method may be used by the semiconductor industry to characterize the oxide precipitates after device-processing heat treatments in a batch of wafers.

Yield implications and scaling laws for submicrometer devices

Yield scaling laws are developed that are applicable to VLSI (very large-scale integration) devices with features of minimum dimension smaller than that at which the defect-size probability density function peaks. Expressions for the fault-probability kernel of reduced-size devices are derived in terms of the full-size or prototype device. The role of the defect-size probability density function with respect to the average fault probability is explained and expressions for it are developed. The ensuing scaling laws are utilized to obtain expressions for the expected number of faults, and then applied to the evaluation of the yield for several different cases. The implications of the results for yield and productivity are examined.< <ETX xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">&gt;</ETX>

Future trends of cross-sectional transmission electron microscopy for electronic and photonic devices

Cross-sectional transmission electron microscopy (XTEM) has played an important role in silicon very large scale integration (VLSI) device development, process evalution and failure analysis. More recently, XTEM has also been applied to photonic device evaluation and diagnosis. Most diffuculties in XTEM sample preparation for both silicon VLSI and photonic devices have been overcome. Sample preparation time is now limited by the nature of ion milling. It is clear that XTEM is more time consuming and expensive than other analytical techniques (Auger spectroscopy, secondary ion mass spectrometry, Rutherford backscattering etc.) and considerable development and refinements of preparation techniques will occur. In this paper new preparation methods are discussed including (1) polyimides both to bond and to protect specimens at elevated temperatures for in situ studies, (2) selective dry ethcing prior to ion milling in order to reduce the effects of preferential sputtering rates, (3) oxide and junction delineation techniques and (4) a precision cross-section method to aid in the diagnosis of specific predefined areas.

Reactive ion etching of polysilicon and tantalum silicide : W. Beinvogl and B. Hasler. Solid St. Technol., 125 (April 1983)

This chapter discusses the technological advantages of high-electron-mobility transistor (HEMT). It describes an HEMT technology for very-large-scale integration (VLSIs) including material, device fabrication, and characteristics for device modeling. Current work and recent advances in HEMT logic and memory integrated circuits (ICs) are reviewed. The future performance of HEMT VLSIs for ultrahigh- speed computer applications is projected. HEMTs are very promising devices for VLSIs, especially operating at liquid nitrogen temperatures, because of their ultra-high speed and low power dissipation. The projected HEMT performance target suitable for VLSIs is a fundamental switching delay below 10 ps with a power dissipation of about 100 μW per stage under 1 μm design rule technology. By evaluating the gate length dependence of threshold voltage and K factor of short-channel HEMTs, short-channel effects were found not to be a problem in microstructures of submicrometer dimensions. Master - slave flip-flop divide - by- two circuits achieved internal logic delays of 22 ps/gate at 77 K and 36 psfgate at 300 K, at an average fan-out of about 2. HEMT technology has been shown to have desirable features for high-performance VLSI devices. A HEMT 1 kbit static RAM has been developed and has achieved an address access time of 0.87 ns to demonstrate the feasibility of high-performance VLSIs. Using the same technology, a HEMT 4 Kb sRAM has also been successfully fabricated and normal read/write operation confirmed.

Electrical surface properties of semi-insulating and ion implanted GaAs revealed by thermo-optical acousto-electric voltage method : K. Varahramyan and P. Das. Solid-St. Electron.25 (6), 517 (1982)

This chapter discusses the technological advantages of high-electron-mobility transistor (HEMT). It describes an HEMT technology for very-large-scale integration (VLSIs) including material, device fabrication, and characteristics for device modeling. Current work and recent advances in HEMT logic and memory integrated circuits (ICs) are reviewed. The future performance of HEMT VLSIs for ultrahigh- speed computer applications is projected. HEMTs are very promising devices for VLSIs, especially operating at liquid nitrogen temperatures, because of their ultra-high speed and low power dissipation. The projected HEMT performance target suitable for VLSIs is a fundamental switching delay below 10 ps with a power dissipation of about 100 μW per stage under 1 μm design rule technology. By evaluating the gate length dependence of threshold voltage and K factor of short-channel HEMTs, short-channel effects were found not to be a problem in microstructures of submicrometer dimensions. Master - slave flip-flop divide - by- two circuits achieved internal logic delays of 22 ps/gate at 77 K and 36 psfgate at 300 K, at an average fan-out of about 2. HEMT technology has been shown to have desirable features for high-performance VLSI devices. A HEMT 1 kbit static RAM has been developed and has achieved an address access time of 0.87 ns to demonstrate the feasibility of high-performance VLSIs. Using the same technology, a HEMT 4 Kb sRAM has also been successfully fabricated and normal read/write operation confirmed.

Susceptibility of semiconductor devices to thermal second breakdown : N. S. Cohn. Proc. IEEE Reliab. Phys. Symp. 90 (1974)

Recent advances in polymeric materials and integrated circuit (IC) encapsulants have made high-reliability very large-scale integration (VLSI) plastic packaging a reality. High-performance silicone gel possesses excellent electrical and physical properties for IC protection. With their intrinsic low modulus and soft gel-like nature, silicone gels have become very effective encapsulants for larger, high I/O, wire-bonded and flip-chip VLSI chips. Furthermore, the recently developed silica-filler modified epoxies, with the well-controlled thermal coefficient of expansion (TCE), have enhanced the flip-chip and chip-on-board hybrid IC encapsulation. Recent studies indicate that, with adequate IC chip surface protection with high-performance silicone gels and epoxies, plastic packages could replace conventional ceramic hermetic packages. This paper reviews the IC technological trends, and IC encapsulation materials and processes. Special focus is placed on the high-performance silicone gel, epoxies and polyimides, their chemistry and use as VLSI device encapsulants for single and multi-chip module applications.