Vertical Transistor Structure Research Articles

Design, Simulation and Optimization of an Enhanced Vertical GaN Nanowire Transistor on Silicon Substrate for Power Electronic Applications

A new vertical transistor structure based on GaN nanowire is designed and optimized using the TCAD-Santaurus tool with an electrothermal model. The studied structure with quasi-1D drift region is adapted to GaN nanowires synthesized with the bottom-up approach on a highly n-doped silicon substrate. The electrical performance is studied as a function of various epi-structure parameters, including region lengths and doping levels, nanowire diameter, and the impact of the surface states. The results reveal that the optimized structure has a Normally-OFF mode with a threshold voltage higher than 0.8 V and exhibits minimized leakage current, low on-state resistance, and maximized breakdown voltage. To the best of our knowledge, this is the first exhaustive study of GaN-based nanowire transistors, providing valuable insights for the scientific community and contributing to a deeper understanding of the impact of GaN nanowire parameters on device performance.

45‐2: Invited Paper: Towards High‐Performance Organic Transistors for Display and other Applications

Organic semiconductor devices have potential for displays as light emitter and organic backplane transistors. We present vertical transistor structures with very short channel length without micropatterning. These devices are well suited to drive organic light‐emitting diodes (OLED), allowing all‐organic flexible displays. We have achieved kA/cm2 current densities useful for bright OLED displays and record operating frequencies >40MHz /2/. Vertical organic light‐emitting transistors show efficient emission in different colors, combining OLED operation and switching and fully compatible with vacuum mass production. Vertical transistors have GHz potential using highly ordered layers grown quasi‐epitaxially.

Many-Tier Vertical GAAFET (V-FET) for Ultra-Miniaturized Standard Cell Designs Beyond 5 nm

The GAAFET (gate-all-around FET) is expected to replace FinFETs in future nodes due to its excellent channel controllability. It is also expected to be an impressive device due to its horizontal or vertical transistor structures. Vertical GAAFETs (V-FETs) are expected to be a promising device compared to horizontal GAAFETs (H-FETs) due to their structure, which allows area reduction and significant parasitic reduction. Besides, V-FETs are positioned on top of each other and thus allow more significant size reductions. Therefore, this paper studies the overall potential of many-tier V-FETs by investigating the essential design factors from the layout perspective. First, we study the factors that should be considered for designing many-tier V-FETs. Second, we propose an interconnect structure that maximizes the advantages of many-tier V-FETs. Third, we compare 2-tier V-FET standard cells to one-tier V-FET cells and visualize the advantages that many-tier V-FET cells provide. Our study shows that 2-tier V-FET standard cells provide a -35.6% area reduction with a cost of +16.5% wirelength and +13.2% parasitic capacitance increase compared to 1-tier V-FET cells. Compared to H-FETs and FinFETs, our cells show -50.1% area reductions with -0.3% wirelength reductions and -18.9% parasitic capacitance reductions. We emphasize that the design freedom to place transistors on top of each other and proper interconnect structures lead to ultra-scale miniaturized standard cell designs. We note that the increase in wirelength and capacitance is due to the vertical size increases and detours that must exist in the designs. Thus, careful circuit design is required to obtain the maximum advantages from V-FETs.

Middle Electrode in a Vertical Transistor Structure Using an Sn Layer by Thermal Evaporation

We report a process for performing the middle electrode for a vertical field effect transistor (VOFET) by the evaporation of a tin (Sn) layer. Bare aluminum oxide (Al2O3), obtained by anodization, and Al2O3 covered with a polymethylmethacrylate (PMMA) layer were used as the gate dielectric. We measured the electrical resistance of Sn while the evaporation was carried out to find the best condition to prepare the middle electrode, that is, good lateral conduction associated with openings that give permeability to the electric field in a vertical direction. This process showed that 55 nm Sn thick is suitable for use in a VOFET, being easier to achieve optimal thickness when the Sn is evaporated onto PMMA than onto bare Al2O3. The addition of a PMMA layer on the Al2O3 surface modifies the morphology of the Sn layer, resulting in a lowering of the threshold voltage. The values of threshold voltage and electric field, VTH = − 8 V and ETH = 354.5 MV/m respectively, were calculated using an Al2O3 film 20 nm thick covered with a 14 nm PMMA layer as gate dielectric, while for bare Al2O3 these values were VTH = − 10 V and ETH = 500 MV/m.

High Performance Flexible Nonvolatile Memory Based on Vertical Organic Thin Film Transistor

AbstractFlexible floating‐gate organic transistor memory (FGOTM) is a potential candidate for emerging memory technologies. Unfortunately, conventional planar FGOTM suffers from weak driving ability and insufficient mechanical flexibility, which limits its commercial application. In this work, a novel flexible vertical FGOTM (VFGOTM) is reported. Benefitting from new vertical architecture, VFGOTM provides ultrashort channel length to afford an extremely high current density. Meanwhile, VFGOTM devices exhibit excellent memory performance and outstanding retention property. The memory properties of VFGOTM devices are comparable or even better than traditional planar FGOTM and much better than the reported organic nonvolatile memory with vertical transistor structures. More importantly, organic nonvolatile memory with vertical transistor structures is investigated for the first time on a flexible substrate. The results show that VFGOTM architecture allows vertical current flow across the channel layer to effectively eliminate the effect of mechanical bending during current transport, which significantly improves the mechanical stability of the flexible VFGOTM. Hence, with a combination of excellent driving ability, memory performance, and mechanical stability, VFGOTM devices meet the practical requirements for high performance memory applications, which have great potential for the application in a wide range of flexible and wearable electronics.

Direct and exchange Coulomb energies in CdSe/ZnSe quantum dots

AbstractWe have determined the direct and exchange electron–electron and electron–hole Coulomb energies in CdSe/ZnSe quantum dots. The experiments are based on single dot photoluminescence at low temperature. By controlling the charging with a vertical transistor structure and by applying a symmetry‐breaking magnetic field, we show how we can determine all the Coulomb energies. The direct Coulomb energies are responsible for large, ∼20 meV, red‐shifts of the emission on charging. The exchange Coulomb energies lead to a very pronounced fine structure splitting, up to 2.6 meV, for the neutral exciton. (© 2006 WILEY‐VCH Verlag GmbH & Co. KGaA, Weinheim)

Modified three terminal charge pumping technique applied to vertical transistor structures

Vertical metal-oxide-semiconductor field-effect transistors (MOSFETs) have evolved into dominant members in the power transistor family. Reliability issues continue to be a major concern, as economic requirements drive towards miniaturization, and higher power ratings for these devices. The charge pumping method offers a simple, direct and powerful way of assessing interface damage for planar structures. Absence of an independent substrate contact in the vertical power structure implies that conventional charge pumping, which requires a substrate contact as well as three additional contacts to the remaining terminals of the MOSFETs, cannot be applied directly to these devices. In this article, we propose an adaptation of the charge pumping technique that enables its application to three terminal devices, in general. The modified form of charge pumping was applied to assess effects of Fowler–Nordheim stressing on production level U-shaped trench-gated MOSFETs. A good correlation between transfer characteristic measurements and the proposed method has been observed.

Pseudo-metal-base transistor with high gain

We use evaporated C60 fullerene as emitter, a conducting polymer blend as base, and Si as collector in a vertical transistor structure similar to a metal-base transistor. The conducting polymer blend used as a base is poly(3,4-ethylenedioxythiophene): poly(styrenesulfonate). The measured common-base current gain of our pseudo-metal-base transistor (p-MBT) is close to 1.0. The p-MBT is straightforward to fabricate and is compatible with conventional Si-based electronics.

Amorphous silicon thin-film transistors with 90° vertical nanoscale channel

This letter reports 100nm channel length vertical thin-film transistors (VTFTs) in hydrogenated amorphous silicon (a-Si:H) technology. The channel length is defined by means of a dielectric film thickness, realized by an anisotropic reactive ion etching process to yield a 90° vertical transistor structure. Furthermore, the device area of the vertical TFT structure is less than ∼1∕3 that of the ubiquitous lateral TFT structure. The 100nm channel length VTFTs exhibit an ON/OFF current ratio of 108, a threshold voltage of 2.8V, and a subthreshold slope of 0.8V∕dec.

Organic-metal-semiconductor transistor with high gain

We use evaporated C60 as the emitter in a vertical transistor structure with Au base and Si collector. The proportion of emitted electrons that overcome the barrier is measured as at least 0.99. Our metal-base transistor is easy to fabricate as it does not involve wafer bonding or require perfect semiconductor-on-metal growth.

NeoSilicon materials and silicon nanodevices

We propose a novel material NeoSilicon, in which both particle size and interparticle distance of nanocrystalline silicon (nc-Si) quantum dots are precisely controlled. New functions in electron transport, photon emission and electron emission are expected due to quantum effects at room temperature and large interaction between dots. The bandgap is determined by the particle size. The conductivity is controlled mainly by tunneling processes. The transport characteristics are also controlled by charge quantization effect. We present fabrication and characterization of NeoSilicon. Based on the idea of separation of the nucleation and the growth processes in plasma decomposition of silane, we have successfully prepared nc-Si particles of 8 nm in diameter with size dispersion of 1 nm, whose surfaces are covered by naturally formed oxide of 1.5 nm thickness. Further reduction of dot size is achieved to 4 nm using self-limiting oxidation processes. Single electron transport characteristics of nc-Si are demonstrated in both planar and vertical transistor structures. Highly efficient electron emission is observed in NeoSilicon samples. Photoluminescence intensity enhancement due to no-phonon-assisted indirect transition is observed in strongly confined nc-Si dots covered by oxide.

Injection transistor-transistor logic (i.t.t.l.)

A new circuit is described that comprises a lateral-multiemitter vertical transistor structure and an inverter transistor. The circuit acts as an injection transistor-transistor logic (i.t.t.l.).