In this talk, I will show our recent achievements for GaN p-n junction diodes with 3.48 kV and 0.95 mΩ·cm2: a record high figure-of-merit (BV2/Ron ) of >12.8 GW/cm2, 600 V GaN vertical V-trench MOSFETs with MBE regrown channel and GaN vertical nanowire and Fin power MISFETs. I. Introduction GaN has been long touted as a promising material for compact and efficient power electronics, owing to its large critical field (>10× of Si), high electron mobility (~2000 cm2/Vs at a carrier concentration of ~1×1016cm-3) and high thermal conductivity (~ 2× of Si). Nowadays GaN vertical power transistors have gained increasing interest in recent years due to the advantagesover lateral transistors in high voltage/high current applications. II. Device fabrication and results A. GaN-on-GaN p-n power diodes The GaN p-n junction epi-structures were grown by MOVPE on bulk-GaN substrates. As shown in Fig.1, three device layer structures have been grown with a varying n-GaN drift layer thickness of 20, 25 and 32 μm. For the 20 μm epi-design, the drift layer doping concentration was kept constant, which is confirmed by the capacitance-voltage (C-V) measurement on these power diodes; the net ND-NA concentration extracted from C-V measurements showed a constant value of 5×1015 cm-3 in the top 10 μm. For the 25 and 32 μm epi-designs, the top 6 μm of the n-GaN drift layer was grown to have the lowest doping concentration: a net ND-NA concentration of ~1×1015 cm-3 was extracted from C-V measurements while a Si concentration of 2.5×101 5 cm-3 was measured by SIMS on a similar epi-wafer. For the 2nd n-GaN drift layer, a net ND-NA concentration of 2~3×1015 cm-3 was extracted in both the 25 and 32 μm power diodes. The benchmark plot is shown in Fig. 2, demonstrating a record Baliga’s figure of merit of >12 GW/cm2 obtained in the 32 μm epi-design.Also shown is that the p-n power diode BV increases with the increasing n-GaN drift-layer thickness while Ron remains nearly the same ~1.0 mΩ·cm2. If the minority carrier lifetime is short, a p-n diode can be assumed to operate like a unipolar device thus Ron is dominated by the n-GaN drift region. Assuming a carrier concentration of 5×1015 cm-3 and a mobility of 2000 cm2/Vs, the specific resistance of a 20 μm n-GaN drift layer is calculated to be ~1.25 mΩ·cm2. The observed record low Ron might arise from other mechanisms including high level injection, photon recycling effects, which warrants further investigation. B. GaN Vertical V-trench MOSFETs The schematic of the device is shown in Fig. 3, which consists of a MBE regrown UID GaN channel covering the sidewall of the V-shaped trench.On-off ratio of 109 and normally-off operation with a threshold voltage of ~16 V is achieved. The output characteristics in Fig. 4 show goodsaturation behavior and an on-current of ~18 A/cm2 at Vgs =25 V. Ron is determined from the linear region to be 0.3 Ω·cm2. The relatively poor Ron and Ion is determined to be limited by the lateral portion of the regrown channel from gated-TLM measurement. We found the sheet resistance of the lateralregrown channel to be ~2 MΩ/sq. at Vgs =25 V. Since the lateral channel length Lg , lateral is 3~4 μm in the measured device, Ron is dominated by the lateral channel. The high resistivity of the lateral regrown channel is likely due tothe carrier compensation by Mg diffusion from the p-GaN underneath. A thicker UID channel or growing a thin n+-GaN counter layer before the channel regrowth could improve the channel conductivity dramatically and is being investigated. The off-state characteristics in shown in Fig. 5. Low drain leakage and a BV of 596 V ismeasured with Vgs =-15 V, indicating good quality of the regrowth p-n junction interface. C . GaN vertical nanowire and fin power MISFETs The NWs and Fins are formedby a top-down approach: dry etch followed by a hot TMAH wet etch to form vertical side walls. Images of fabricated NWs are shown in Fig. 6. The output characteristics of the Fin-MISFET are shown in Fig. 7. An on-current of 14 kA/cm2 and Ron of 0.4 mΩ·cm2 are extracted. The off-state characteristics of the Fin-MISFETs under different gate-bias is shown in Fig. 8. Under more negative gate-bias, the breakdown voltage of the same device increases, reaching a highest value 513 V under Vgs =-15 V where the device undergoes a hard breakdown. Acknowledgement: This work was supported in part by the ARPA-E SWITCHES program (DE-AR0000454) and carried out at the Cornell Nanoscale Science and Technology Facilities(CNF) sponsored by the NSF NNCI program (ECCS-15420819) and New York State. Figure 1
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Mar 9, 2020
Toshiyuki Horiuchi + 3
Open Access