Vertical Power MOSFET Research Articles

Influence of ion beam energy on SEGR failure thresholds of vertical power MOSFETs

For the first time, experimental observations and numerical simulations show that the impact energy of the test ion influences the single-event gate rupture (SEGR) failure thresholds of vertical power MOSFETs. Current testing methodology may produce false hardness assurance.

The use of charge-pumping for characterizing irradiated power MOSFETs

A charge-pumping technique is proposed for characterizing radiation-induced interface traps in vertical power MOSFETs. An original setup allowing measurements on these 3-contact devices is presented. The first experimental results before and after irradiation are discussed.

Experimental studies of single-event gate rupture and burnout in vertical power MOSFETs

Numerous studies have revealed that vertical power MOSFETs are susceptible to single-event burnout (SEB) and single-event gate rupture (SEGR), resulting in degraded performance or even catastrophic failure when operated in a cosmic-ray environment like space. This paper summarizes many of those experimental studies and examines the problems, test methodologies, and experimental results. Previously unavailable information on SEGR is also provided.

Single-event gate rupture in vertical power MOSFETs; an original empirical expression

An empirical expression is derived that describes the susceptibility of a power double-diffused metal-oxide semiconductor (DMOS) field-effect transistor (FET) to single-event gate rupture (SEGR) induced by the interaction of mono-energetic ions with regions of the n-epi, gate oxide, and polysilicon gate. Using this expression, the failure threshold voltages for the gate and drain can be analytically determined for any particular value of energy deposition along the ion's path or more commonly described as the ion's linear energy transfer (LET) function. This paper delineates our research, an in-depth study of vertical power DMOS transistors, having a 50-nm gate oxide and a strong SEGR response, subjected to various mono-energetic ions, representing particular values of LET between 0 and 83 MeV cm/sup 2/ mg/sup -1/. A description of the devices characterized, the test setup and test methodology employed, the failure threshold voltages measured, and the analysis techniques used are all summarized. Finally, an empirical equation is presented that portrays the locus of SEGR in the {-V/sub GS/, V/sub DS/} plane for all values of LET. >

SiC devices: physics and numerical simulation

The important material parameters for 6H silicon carbide (6H-SiC) are extracted from the literature and implemented into the 2-D device simulation programs PISCES and BREAKDOWN and into the 1-D program OSSI Simulations of 6H-SiC p-n junctions show the possibility to operate corresponding devices at temperatures up to 1000 K thanks to their low reverse current densities. Comparison of a 6H-SiC 1200 V p-n/sup -/-n/sup +/ diode with a corresponding silicon (Si) diode shows the higher switching performance of the 6H-SiC diode, while the forward power loss is somewhat higher than in Si due to the higher built-in voltage of the 6H-SiC p-n junction. This disadvantage can be avoided by a 6H-SiC Schottky diode. The on-resistances of Si, 3C-SiC, and 6H-SiC vertical power MOSFET's are compared by analytical calculations. At room temperature, such SiC MOSFET's can operate up to blocking capabilities of 5000 V with an on-resistance below 0.1 /spl Omega/cm/sup 2/, while Si MOSFET's are limited to below 500 V. This is checked by calculating the characteristics of a 6H-SiC 1200 V MOSFET with PISCES. In the voltage region below 200 V, Si is superior due to its higher mobility and lower threshold voltage. Electric fields in the order of 4/spl times/10/sup 6/ V/cm occur in the gate oxide of the mentioned 6H-SiC MOSFET as well as in a field plate oxide used to passivate its planar junction. To investigate the high frequency performance of SiC devices, a heterobipolartransistor with a 6H-SiC emitter is considered. Base and collector are assumed to be out of 3C-SiC. Frequencies up to 10 GHz with a very high output power are obtained on the basis of analytical considerations.< <ETX xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">&gt;</ETX>

Effect of partial ionization and the characteristics of lateral power diamond MESFETs

Power device structures, which could be implemented by using diamond technology of today, have been analyzed with the aid of a two-dimensional numerical simulator code for semiconductor devices. It has been found that partial ionization of deep acceptor states substantially degrades the electrical performance of 1000 V lateral diamond power MESFETs. No advantage over corresponding silicon devices can be obtained. If the partial ionization phenomenon can be eliminated, the on-resistance of the diamond MESFET is almost two orders of magnitude smaller than in vertical silicon power MOSFETs having the same breakdown voltage.

High Power and High Frequency Silicon Carbide Devices

ABSTRACTThe breakdown electric field of 4H-SiC as a function of doping was measured using pn junction rectifiers, with maximum voltages of 1130 V being achieved. 4H-SiC vertical power MOSFET structures have shown specific on-resistances of 33 mΩ-cm2 for devices capable of blocking 150 V. A current density of 100 A/cm2 was achieved at a drain voltage of 3.3 V. Thyristors fabricated in SiC have also shown blocking voltages of 160 V and 100 A/cm2 at 3.0 V. High temperature operation was measured, with the power MOSFETs operating to 300°C, and the thyristors operating to 500°C.Submicron 6H- and 4H-SiC MESFETs have shown good I-V characteristics to Vd= 40 V, with an Idss of 200–300 mA/mm. The maximum operating frequencies (fmax) achieved for 6H-SiC MESFETs is 13.8 GHz, with small-signal power gains of 9.8 dB and 2.9 dB at 5 GHz and 10 GHz, respectively. 4H-SiC MESFETs have demonstrated an RF output power density of 2.8 W/mm at 1.8 GHz. This is the highest power density ever reported for SiC and is 2–3 times higher than reported for comparable GaAs devices.

Demonstrating the potential of 6-H silicon carbide for power devices

Discusses the first vertical UMOS power MOSFETs ever reported in SiC, shows the highest gain 6H-SiC BJTs (bipolar junction transistors) and thyristors ever reported, and demonstrate the high-temperature operation of these devices. Vertical power MOSFETs fabricated in 6H-SiC with a UMOS design have specific on-resistances as low as 38 m Omega -cm/sup 2/ at a gate bias of +12 V. These devices can have current densities as high as 190 A/cm/sup 2/ (0.32 A/cm of gate periphery) and can dissipate a maximum power density of 5.4 kW/cm/sup 2/. SiC BJTs have been demonstrated up to 400 degrees C. The device structure used a reactive ion etched emitter with sintered Ni contacts to both the emitter and collector, and Al/Ti alloy contacts to the base. Four-layer structures have also been demonstrated in 6H-SiC, with p-n-p-n thyristors showing 100 V operation.

An intelligent power IC with double buried-oxide layers formed by SIMOX technology

A device structure for an intelligent power LSI composed of a vertical power MOSFET and a control CMOS LSI on a single chip is discussed. The distinctive feature of the device structure is that double buried-oxide layers formed by SIMOX technology are utilized to electrically protect the CMOS LSI from the high voltage applied to the power MOSFET. An evaluation of the electrical characteristics of an intelligent power IC and its components fabricated on a trial basis for automotive applications verifies the usefulness of the device structure.< <ETX xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">&gt;</ETX>

Optimized trench MOSFET technologies for power devices

Low-voltage silicon trench power MOSFETs with forward conductivities approaching the silicon limit are reported. Vertical trench power MOSFETs with the measured performances of V/sub DB/=55 V (R/sub sp/=0.2 m Omega -cm/sup 2/, k/sub D/=5.7 Omega -pF) and V/sub DB/=35 V (R/sub sp/=0.15 m Omega -cm/sup 2/, k/sub D/=4.3 Omega -PF) were developed where V/sub DB/ is the drain-source avalanche breakdown voltage, R/sub sp/ is the specific on-state resistance, and k/sub D/=R/sub sp/C/sub sp/ is the input device technology factor where C/sub sp/ is the specific MOS gate input capacitance. The optimum device performance resulted from an advanced trench processing technology that included (1) an improved RIE process to define scaled vertical silicon trenches, (2) silicon trench sidewall cleaning to reduce the surface damage, and (3) a novel polysilicon gate planarization technique using a sequential oxidation/oxide etchback, process. The measured performances are shown to be in excellent agreement with the two-dimensional device simulations and the calculated results obtained from an analytical model. >

Optimally scaled low-voltage vertical power MOSFETs for high-frequency power conversion

The systematic optimization of low-voltage silicon power MOSFET technology is described. It is shown that device scaling using advanced fabrication technologies can result in nearly optimal performance from low-voltage silicon power MOSFETs. The details discussed include: (1) system impact; (2) unit cell optimization; (3) device and process modeling; (4) fabrication technology development; and (5) performance results. The device technologies optimized include 30-, 50-, and 100-V vertical power DMOSFETs with optimally scaled gate polysilicon and source/drain contacts. Devices with the lowest specific on-resistance, the lowest specific input capacitance, and improved high-frequency switching performance have been fabricated with excellent wafer yield. This is the first successful demonstration of device scaling and its impact on performance of high-voltage and smart-power technologies.< <ETX xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">&gt;</ETX>

A 50-V, 0.7-m Omega *cm/sup 2/, vertical-power DMOSFET

A 50-V vertical power MOSFET with extremely low specific on resistance is reported. Devices with a cell density as high as 8 million cells/in/sup 2/ and capable of switching 160 A of current have been successfully fabricated using an improved fabrication technology which used low processing temperatures, double-layer interlevel dielectric, shallow source implants, and an improved source contact metallurgy. The lowest measured specific on resistances are 0.8 and 0.7 m Omega *cm/sup 2/, respectively, under continuous and pulsed bias conditions for FETs capable of blocking 50 V in the reverse direction. This result represents the best ever reported forward conductivity for a 50-V power MOSFET.< <ETX xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">&gt;</ETX>

Latch-back-free self-aligned power MOSFET structure with silicided source and body contact

A self-aligned vertical double-diffused power MOSFET structure with a very small source region formed by outdiffusion of phosphorous from the sidewall phosphosilicate glass (PSG) is proposed. The proposed structure eliminates the latch-back phenomena and also reduces the chip area. The first experimental results of the proposed structure fabricated with the mask set for a conventional device show latch-back-free I-V characteristics.< <ETX xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">&gt;</ETX>

Numerical and experimental comparison of vertical DMOSFET and UMOSFET

A numerical analysis has been performed to evaluate the relative performance of DMOS and UMOS power FETs based on a two-dimensional analytical approach. Since termination technology can achieve a near-ideal breakdown voltage for a given substrate resistivity and thickness, the breakdown voltage is determined by the intrinsic geometry of the unit cell in the vertical power MOSFETs (DMOSFET and UMOSFET). The authors analyse the on-resistance value each structure can offer while satisfying a specific blocking voltage requirement is given.< <ETX xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">&gt;</ETX>

Optimum design of vertical power MOSFET with thick drain oxide

AbstractThe optimum design of a vertical power MOSFET with thick drain oxide is described, taking into account such dc characteristics as the on‐resistance and breakdown voltage.Introducing the empirical ideality of the edge‐termination which determines the breakdown voltage of the device, the optimum doping density and thickness of the epitaxial layer have been determined to minimize the on‐resistance.Using two‐dimensional simulation to evaluate the optimum design of the device, the thickness of the drain oxide and the relationship between the layout pitch and the product of on‐resistance and active area have been determined. As a result, the following conclusions have been obtained.1) Based on the ideality for the edge‐termination, the optimum combination between the thickness and the doping density of the epitaxial layer can be determined.2) The optimum layout pitch depends on the decrease in the electron concentration in the accumulation layer at the drain surface and the parasitic JEET effect.3) The optimum layout pitch decreases as the thickness of the drain oxide increases.Finally, the design of a vertical MOSFET with a breakdown voltage of 500 V will be described.

A new vertical power MOSFET structure with extremely reduced on-resistance

A new vertical power MOSFET structure called rectangular-grooved MOSFET (RMOS) is proposed, in which the vertical channels are provided along the sidewalls of the rectangular grooves formed by a reactive ion-beam etching (RIBE) technique. The structure is characterized by reduced ON-resistance and high packing density. The relationship between the ON-resistance and the packing density in the new structure is calculated. It is demonstrated that the structure essentially possesses a lower ON-resistance per unit area than VMOS and DMOS structures. Experimental results are also described in detail.

Power MOSFET dynamic large-signal model

A large-signal dynamic circuit model for the double-diffused vertical power MOSFET is reported. The model is physically based and its parameters are readily determined from static curve tracer measurements and small-signal measurements using simple data-reduction techniques. The equivalent circuit can be implemented in general purpose nonlinear circuit analysis computer programs, such as SPICE 2, for use in the analysis and design of switching circuits. The accuracy of the model is verified by the excellent correlation obtained between detailed simulated and measured switching characteristics on an experimental high-speed switching circuit.

A large angle electrostatic deflection, variable shaped, electron beam exposure system

In electron beam direct writing, a capability of ‘‘one chip within one deflection field’’ can reduce time wasted in stage moving, and eliminate field stitching errors in a chip. These advantages lead to high throughput and high overlay accuracy for successful VLSI fabrications. A large angle electrostatic deflection, variable shaped, electron beam exposure system (EB57) has been developed to achieve this capability. The key EB57 technologies are a large angle electrostatic deflection and high speed deflection control. Newly developed multiple electrostatic deflectors were designed using an in‐lens, dual channel deflection method. In this method, two types of field and subfield deflectors are equipped inside a projection lens. Deflectors free of third and fifth θ components can provide a large angle of deflection with a 10 mm2 field. 18‐bit digital‐to‐analog converters, and ±800 V amplifiers effect this large field deflection. The high breakdown voltage for the amplifiers is attained by connecting vertical power MOSFETs in series. The settling time of the amplifiers is less than 10 μs at 1/64 full scale. Amplifiers for subfield scanning and beam shaping have a 250 ns settling time at full scale. To correct chip distortions, deflection distortions, and stage positioning errors, a new data correction method that takes rounding off errors into consideration has been applied to a high speed arithmetic unit. This EB57 system can write from 7 to 10 4‐in. wafers per hour with 0.5 μm lithography.

Second breakdown of vertical power MOSFET's

It is shown that a phenomenon of second breakdown similar to that in bipolar transistors can occur in vertical power MOSFET's. A model for the phenomenon of second breakdown involving the avalanche multiplication of the channel current, the parasitic bipolar transistor, and base resistance is proposed. After presenting the theory, this model is compared with experiments on four-terminal V-groove test devices in which the substrate can be accessed independently. Good agreement is achieved between calculated and measured boundaries of the safe operating area. The model should be applicable to DMOS devices as well.

A 600-volt MOSFET designed for low on-resistance

A 600-V vertical power MOSFET with low on-resistance is described. The low resistance is achieved by means of achieving near-ideal drain junction breakdown voltage and reduced drain spreading resistance from the use of an extended channel design. The various tradeoffs inherent in the design are discussed. Both calculated and experimental data are presented. The remote source configuration of the experimental device is also discussed.