Vertical Flash Memory Research Articles

A Study on the Channel Holes’ Diameter Effects of High-Performance Vertical-Channel Flash Memory Cells

Abstract High-performance vertical-channel flash (HVF) memory cells were fabricated on the single crystalline Si (c-Si) sidewalls of the cylindrical deep wells in c-Si substrate. To investigate the diameter effects of the cylindrical deep wells, namely channel holes, on HVF cells, the channel holes with different diameters, ranging from 65 nm to 260 nm, were made. Memory gate stacks of SiO2/ Al2O3/HfO2/Al2O3/TiN/W were formed by ozone oxidation and then ALD with the deposition thicknesses of 1/5/7/8/2/150 nm, respectively. For the devices with their diameters equal to or greater than 150 nm, their electrical properties, such as Vt, SS, DIBL, and program/erase characteristics, are close. As expected, DIBL and SS become better as the diameter increasing due to better gate control with larger diameter. However, large changes were occurred for the devices with the diameters of 90 nm and 65 nm. A simple model based on cylinder bulk for vertical flash memory devices was presented to obtain an approximate analytical solution for depletion-width and explain our experimental data. For the devices with the diameters of 150 nm, the high On/Off current ratio of 107 and relatively large memory window of 4.5 V were achieved. However, programming/erasing efficiency were degraded with hole diameter decreasing.

Scaling Challenges of Floating Gate Non-Volatile Memory and Graphene as the Future Flash Memory Device: A Review

With the increasing number of electronic consumer and information technology, demands for non-volatile memory rapidly grow. This study comprehensively reviewed the challenges related to the floating gate transistor for each component of the gate stack that consists of the tunnel oxide layer, inter-poly dielectric (IPD) oxide layer and poly-Si floating gate until reaching its bottleneck as the floating gate thickness scale to 7 nm. By going through the development of flash memory from its early year, the issues of the floating gate structure are identified. In resolving these issues, several approaches and upcoming flash memory devices are proposed. The prospect of carbon-based floating gate devices covering the graphene flash memory (GFM) and the vertical CNTFET floating gate are thoroughly discussed; reviewing its device performance and transient characteristics, which were extracted from experimental works and compared with recent upcoming technologies such as the HFG and the three-dimensional (3D) vertical flash memory. Reports indicate that graphene flash memory (GFM) capable of rivaling with the upcoming hybrid floating gate (HFG) device. It is found that the carrier concentration, transient characteristics and memory window of GFM are very much comparable to the HFG. Attributes to the high density of states (DOS) of graphene, GFM managed to lower its operating voltage while achieving comparable memory window as HFG. In the case of CNTFET with nanocrystal floating gate, the device performance is lesser than the 3D vertical flash memories in terms of its short channel effect and gate capacitance ratio. But considering its nanometer structure that has ballistic properties, better device performance with a proper definition of metal contact and synthesis can be achieved. Finally, the advantages of using graphene as floating gate are concluded and future work to improve the CNTFET floating gate is proposed.

Electric Potentials of Vertical Flash Memory with a Macaroni Structure.

This paper presents the analytical electric potentials of vertical flash memory with a macaroni structure derived by solving a one-dimensional Pöisson equation for vertical flash memory. The solution provides the cross-sectional electric potentials between the surface and the inner oxide layer of the polysilicon channel in flash memory. The band bending and the charge density were obtained on the basis of the electric potential of the device, which is an important factor in flash memory operation. Additional parameters for the electric potentials in flash memory with a macaroni structure are described.

3-D Vertical FG nand Flash Memory With a Novel Electrical S/D Technique Using the Extended Sidewall Control Gate

We propose a novel 3-D vertical floating-gate (FG) nand Flash memory cell array with a novel electrical source/drain (S/D) technique using extended sidewall control gates (ESCGs). A cylindrical FG structure is implemented to overcome the reliability issues of charge-trap-type cells. A novel electrical S/D layer by the ESCG structure also allows enhancement-mode operation. With this novel structure, we successfully demonstrate normal Flash cell operation with high-speed programming and superior read currents due to both the increase in coupling ratio and the use of low resistive electrical S/D technique by device simulation. Moreover, we found that the 3-D vertical Flash memory cell array with the novel electrical S/D technique had less interference with neighboring cells by about 50% in comparison with the conventional 3-D vertical FG nand cell array without an ESCG. Above all, the proposed cell array is one of the candidates for a Terabit 3-D vertical nand Flash cell array with high-speed read/program operation and high reliability.

A Novel Sensing Scheme for Reliable Read Operation of Ultrathin-Body Vertical nand Flash Memory Devices

In this brief, an advanced sensing scheme for ultrathin-body vertical Flash memory device is introduced experimentally. Without an increment in the number of read operations, the program/erase states of a memory cell can be identified exactly even with the existence of electrical interference between cells having an ultrathin vertical channel in common. The novel sensing scheme, i.e., the double sensing per 2 bits method, was validated for a fabricated device with a channel thickness of 80 nm. The proposed method can be also used as reference for establishing a smart sensing scheme for multilevel cell NAND Flash memory devices.

Protein-Assembled Nanocrystal-Based Vertical Flash Memory Devices with Al2O3 Integration

This work presents vertical flash memory devices with protein-assembled PbSe nanocrystals as a floating gate and Al2O3 as a control oxide. The advantage of a vertical structure is that it improves cell density. Protein assembly improves uniformity of nanocrystals, which reduces threshold voltage variation among devices. The introduction of Al2O3 as a control oxide provided lower voltage/faster operation and hence less power consumption compared with the devices fabricated with SiO2. The integration of Al2O3 appeared to be compatible with the protein assembly approach. In conclusion, Al2O3 has the potential to become the high-k control oxide due to its relatively high electron/hole barrier heights, and high permittivity.

Vertical Flash Memory Cell With Nanocrystal Floating Gate for Ultradense Integration and Good Retention

We demonstrate a new vertical (3-D) Flash memory transistor cell with nanocrystals as the floating gate on the sidewalls that can form a high-retention ultrahigh density memory array. This scalable vertical cell architecture can allow a theoretical maximum array density of 1/(4F 2), where F is the minimum lithographic pitch, thus circumventing the integration density limitations of conventional planar Flash memory arrays. Discrete SiGe nanocrystals that are grown by conformal chemical vapor deposition process on the pillar sidewalls form the floating gate and render excellent retention properties at room temperature and at 85 degC. The cell shows a large memory window of ~1 V and endurance of more than 105 cycles

Vertical flash memory with protein-mediated assembly of nanocrystal floating gate

The authors propose and demonstrate a vertical flash memory device incorporating protein-mediated ordering of nanocrystal floating gate to help circumvent density scaling and/or performance limitations of planar flash memory with continuous floating gate. The scalability of the vertical architecture can allow the theoretical maximum array density of 1∕4F2 (F: minimum lithographic pitch), thus circumventing the integration density limitations of planar flash transistor arrays. The nanocrystal floating gate renders reasonable retention, while the protein-mediated ordering of nanocrystals allows scalability and manufacturability. With tunneling program/erase, a memory window of 0.5V, endurance >105cycles, and retention beyond 105s is reported.