Vertical Electrical Interconnects Research Articles

Computational Study of the Coupling Performances for a Long-Distance Vertical Grating Coupler

We present a high-efficiency silicon grating coupler design based on a left–right mirror-symmetric grating and a metal mirror. The coupler achieves nearly perfect 90-degree vertical coupling. When two SOI chips are placed face to face with a vertical working distance of 50 μm, the chip-to-chip interlayer coupling efficiency reaches as high as 96%. When the vertical working distance ranges from 45 μm to 55 μm, the coupling loss remains below 1 dB. We also verified the effectiveness of our designed vertical coupler through 3D FDTD full-model simulation. The results demonstrate that our proposed vertical coupling structure represents a high-efficiency solution for 3D optical interconnects. The integration of multiple photonic chips in a 3D package with vertical optical and electrical interconnects is also feasible in the foreseeable future.

Water in contact with the backside of a silicon substrate enables drilling of high-quality holes through the substrate using ultrashort laser pulses.

Holes through silicon substrates are used in silicon microsystems, for example in vertical electrical interconnects. In comparison to deep reactive ion etching, laser drilling is a versatile method for forming these holes, but laser drilling suffers from poor hole quality. In this article, water is used in the silicon drilling process to remove debris and the shape deformations of the holes. Water is introduced into the drilling process through the backside of the substrate to minimize negative effects to the drilling process. Drilling of inclined holes is also demonstrated. The inclined holes could find applications in radio frequency devices.

Research on Wafer-Level MEMS Packaging with Through-Glass Vias.

A MEMS fabrication process with through-glass vias (TGVs) by laser drilling was presented, and reliability concerns about MEMS packaging with TGV, likes debris and via metallization, were overcome. The via drilling process on Pyrex 7740 glasses was studied using a picosecond laser with a wavelength of 532 nm. TGVs were tapered, the minimum inlet diameter of via holes on 300 μm glasses was 90 μm, and the relative outlet diameter is 48 μm. It took about 9 h and 58 min for drilling 4874 via holes on a four-inch wafer. Debris in ablation was collected only on the laser inlet side, and the outlet side was clean enough for bonding. The glass with TGVs was anodically bonded to silicon structures of MEMS sensors for packaging, electron beam evaporated metal was used to cover the bottom, the side, and the surface of via holes for vertical electrical interconnections. The metal was directly contacted to silicon with low contact resistance. A MEMS gyroscope was made in this way, and the getter was used for vacuum maintenance. The vacuum degree maintained under 1 Pa for more than two years. The proposed MEMS fabrication flow with a simple process and low cost is very suitable for mass production in industry.

Double-Sided Process for MEMS SOI Sensors With Deep Vertical Thru-Wafer Interconnects

This paper reports an approach for co-fabrication of silicon-on-insulator (SOI) sensors with low-resistance vertical electrical interconnects in thick (up to $600~\mu \text{m}$ ) wafers. The thru-wafer interconnects double-sided (TWIDS) process is based on bottom-up seedless copper electroplating, and allows for voids-free features and high aspect ratio (wafer thickness to copper diameter ratio of 10:1). This work describes the design trade-offs, process flow, and characterization of interconnects. TWIDS technology is compatible with a standard SOI micro-electro-mechanical systems (MEMS) fabrication process and is applicable for micro sensors, such as accelerometers, gyroscopes, resonators, and RF MEMS devices, as well as for the 3-D MEMS assemblies. As a demonstration of potential applications, miniature toroidal ring gyroscopes were fabricated using the TWIDS process. The experimental characterization showed that the low-resistance interconnects with low parasitic losses are suitable for integration with capacitive-detection sensors. In addition, the mechanical stability of the interconnects is discussed in this paper, and a method to enhance structural rigidity by means of filling the insulating gaps with Parylene C is demonstrated. [2017-0179]

Combined Surface Activated Bonding Technique for Hydrophilic SiO2-SiO2 and Cu-Cu Bonding

Wafer bonding with high quality (such as high strength, void-less interface, and low-resistance vertical electrical interconnects) obtained at low temperatures is highly desired for 3D integration of microsystems. This paper reports a combined surface activated bonding (SAB) technique for improvement of the bonding quality of SiO2-SiO2 pairs bonded at 200°C. The present bonding technique employs a combination of surface irradiation using a Si-containing Ar beam and prebonding attach-detach procedure prior to bonding in vacuum, followed by postbonding annealing in ambient pressure. The bonding method has also been found effective for SiO2-SiNx and Cu-Cu bonding at 200°C. Results of bonding strength measurements, transmission electron microscopy (TEM) and energy-dispersive X-ray spectroscopy (EDS) observations are reported and discussed to understand the present technique. The feasibility of this bonding technique for Cu/SiO2 and Cu/SiO2/SiNx hybrid bonding is also discussed.

Low-Temperature Bonding for Silicon-Based Micro-Optical Systems

Silicon-based integrated systems are actively pursued for sensing and imaging applications. A major challenge to realize highly sensitive systems is the integration of electronic, optical, mechanical and fluidic, all on a common platform. Further, the interface quality between the tiny optoelectronic structures and the substrate for alignment and coupling of the signals significantly impacts the system’s performance. These systems also have to be low-cost, densely integrated and compatible with current and future mainstream technologies for electronic-photonic integration. To address these issues, proper selection of the fabrication, integration and assembly technologies is needed. In this paper, wafer level bonding with advanced features such as surface activation and passive alignment for vertical electrical interconnections are identified as candidate technologies to integrate different electronics, optical and photonic components. Surface activated bonding, superior to other assembly methods, enables low-temperature nanoscaled component integration with high alignment accuracy, low electrical loss and high transparency of the interface. These features are preferred for the hybrid integration of silicon-based micro-opto-electronic systems. In future, new materials and assembly technologies may emerge to enhance the performance of these micro systems and reduce their cost. The article is a detailed review of bonding techniques for electronic, optical and photonic components in silicon-based systems.

Micro-Raman investigation of stress distribution in laser drilled via structures

Through-wafer vertical electrical interconnects (vias) with diameters varied from 15 to 80 μm were formed on Si substrates using a UV diode-pumped solid state laser (355 nm). Micro-Raman spectroscopy was employed for the investigation of stress and structural changes induced in silicon within the heat-affected zone due to laser machining. A maximum stress of ∼300 MPa, as a result of laser drilling, was observed close to the via edge. It was found that the stress decays within a distance of 1–3 μm from the via’s side-wall and that the laser machining did not lead to the formation of amorphous silicon around the via structures.

Analysis of materials modifications caused by UV laser micro drilling of via holes in AlGaN/GaN transistors on SiC

Pulsed UV laser drilling can be applied to fabricate vertical electrical interconnects (vias) for AlGaN/GaN high electron mobility transistor devices on single-crystalline silicon carbide (SiC) substrate. Through-wafer micro holes with a diameter of 50–100 μm were formed in 400 μm thick bulk 4H–SiC by a frequency-tripled solid-state laser (355 nm) with a pulse width of ≤30 ns and a focal spot size of ∼15 μm. The impact of laser machining on the material system in the vicinity of micro holes was investigated by means of micro-Raman spectroscopy and transmission electron microscopy. After removing the loosely deposited debris by etching in buffered hydrofluoric acid, a layer of <4 μm resolidified material remains at the side walls of the holes. The thickness of the resolidified layer depends on the vertical distance to the hole entry as observed by scanning electron microscopy. Micro-Raman spectra indicate a change of internal strain due to laser drilling and evidence the formation of nanocrystalline silicon (Si). Microstructure analysis of the vias’ side walls using cross sectional TEM reveals altered degree of crystallinity in SiC. Layers of heavily disturbed SiC, and nanocrystalline Si are formed by laser irradiation. The layers are separated by 50–100 nm thick interface regions. No evidence of extended defects, micro cracking or crystal damage was found beneath the resolidified layer. The precision of UV laser micro ablation of SiC using nanosecond pulses is not limited by laser-induced extended crystal defects.

Growth and electrical characterization of high-aspect-ratio carbon nanotube arrays

The remarkable properties of carbon nanotubes (CNTs) make them attractive for microelectronic applications, especially for interconnects and nanoscale devices. In this paper, we describe a microelectronics compatible process for growing high-aspect-ratio CNT arrays with application to vertical electrical interconnects. A lift-off process was used to pattern catalyst (Al 2O 3/Fe) islands to diameters of 13 or 20 μm. After patterning, chemical vapor deposition (CVD) was involved to deposit highly aligned CNT arrays using ethylene as the carbon source, and argon and hydrogen as carrier gases. The as-grow CNTs were characterized by transmission electron microscopy (TEM), scanning electron microscopy (SEM) and X-ray photoelectron spectroscopy (XPS). The results demonstrated that the CNTs have high purity, and form densely-aligned arrays with controllable array size and height. Two-probe electrical measurements of the CNT arrays indicate a resistivity of ∼0.01 Ω cm, suggesting possible use of these CNTs as interconnect materials.

Wafer-Scale Microdevice Transfer/Interconnect: Its Application in an AFM-Based Data-Storage System

We have developed a robust, CMOS back end of the line (BEOL) compatible, wafer-scale device transfer, and interconnect method for batch fabricating systems on chip that are especially suitable for MEMS or VLSI-MEMS applications. We have applied this method to transfer arrays of 4096 free-standing cantilevers with good cantilever flatness control and high-density vertical electrical interconnects to the receiver wafer (typically CMOS). Such an array is used in a highly parallel, scanning-probe-based data-storage system, which we internally call "millipede." A very high-integration density has been achieved, even for wafer-scale transfer, thanks to the interlocking nature of the interconnect structure, which provides easy alignment with an accuracy of 2 /spl mu/m. The typical integration density is 100 cantilevers/mm/sup 2/ and 300 electrical interconnects/mm/sup 2/. Note that only the cantilevers, not a chip with cantilevers, are transferred and, unlike flip-chip technology, our method preserves the device orientation, which is crucial for MEMS applications, where often the MEMS device should have access to its environment (in our case, the cantilever tips are in contact with the storage medium). After device transfer, the system is mechanically and electrically stable up to at least 500/spl deg/C, allowing post-transfer wafer processing.

An Approach towards the Printing of Polymer Circuits

ABSTRACTThe combination of soluble polymers with printing and coating techniques enabled the fabrication of polymer field-effect transistors (PFETs) on flexible films. The devices were built in a top gate configuration, with four functional layers deposited. The electrodes were patterned by gravure offset printing, where source-drain were made from conducting polyanilin and carbon black filled conducting ink was used as gate material. The doctor blading technique was utilized for coating low viscosity solutions, where Poly(3-alkyllthiophene) served as active semiconductor material. Thus completely printed PFETs have been demonstrated. Further steps for printing integrated polymer circuits included the fabrication of inverters combined from two printed. Screen-printing could be used as an alternative to coating and has the potential to enable vertical electrical interconnects between top and bottom layer of circuits. To test the suitability insulating layers were screen-printed homogenously onto lithographically patterned electrodes made from gold. The PFETs' yield was sufficient enough to let a 7-stage ring oscillator work with a clock frequency of 4 Hz.

3D Si‐on‐Si stack packaging

A new concept of 3D‐electronic packaging is presented: Si‐on‐Si multi‐chip module flip‐chip technology with arrays of fine etched and filled vertical electrical interconnections (vias). Arrays of vias with a high number of interconnections, and not only peripheral interconnections are used. A 3D Si‐on‐Si stack package demonstrator has been realized consisting of four Si‐substrates each representing a system level and containing four thinned and flip‐chip assembled chips. The chips are flip‐chip mounted on the flat side of the Si‐substrates. When interconnecting the Si‐substrates by bump technology the chips submerge into cavities on the rear side of the adjacent Si‐substrate. The chips also test the technology and quality of the electronic packaging, and therefore contain a set of thin film heaters, junctions for temperature measuring, Al‐meanders for stress and strain measuring and daisy chains for conduction path monitoring.

8 x 8 array of thin-film photodetectors vertically electrically interconnected to silicon circuitry

This paper reports the integration of an 8/spl times/8 array of thin-film GaAs-AlGaAs photodetectors onto a silicon-oscillator array circuit for massively parallel-image processing applications. Each detector was electrically connected to the oscillator below it using vertical electrical interconnections. Both sides of the thin-film devices were metallized for electrical contact, which minimized the interconnection density on the silicon circuit, thereby maximizing the available signal processing area. The yield of this integrated array and associated circuit was 100%, with the majority of pixels demonstrating a dynamic range of 50 dB. >