Vernier Time-to-digital Converter Research Articles

Improved Metastability of True Single-Phase Clock D-Flipflops With Applications in Vernier Time-to-Digital Converters

This paper investigates the metastability of true single-phase clock (TSPC) D flip flops (DFFs) and its impact on the resolution of Vernier time-to-digital converters (TDCs). The mechanisms of the metastability of TSPC DFFs are investigated and the analytical expressions of setup time and hold time are obtained. A shunt capacitor technique capable of reducing setup time and hold time to zero with no power and delay penalty is proposed. The impact of PVT (process, voltage, temperature) on the effectiveness of the proposed technique is quantified using simulation. Vernier TDCs, both right-shifting and left-shifting, with untuned and tuned DFFs are designed in TSMC 130 nm 1.2 V CMOS technology and analyzed using Spectre with BSIM3V3 device models. Simulation results demonstrate TDCs with tuned DFFs enjoy zero conversion error while the right-shifting and left-shifting TDCs with untuned DFFs have 1-bit and 5-bit conversion errors or 11% and 56% error rates, respectively.

An 8.5 ps Resolution, Cyclic Vernier TDC Using a Stage-Gated Ring Oscillator and DWA-Based Dynamic Element Matching in 28 nm CMOS

Herein, we present a cyclic Vernier time-to-digital converter (TDC) using a stage-gated ring oscillator (SGRO) and data-weighted averaging (DWA) dynamic element matching (DEM). Using the phase-preserving characteristic of SGRO, DEM is realized using simple enable switches. DWA is achieved by storing the SGRO’s previous state and using it as the beginning state of the next conversion. This approach achieves cyclic selection of signal propagation paths in SGRO, and the systematic mismatch is averaged out through multiple conversions. DWA achieves the first-order mismatch correction, further improving linearity. Circuit techniques are presented to achieve accurate measurement by removing errors occurring in multiphase time-domain processing. A TDC fabricated with a 28-nm CMOS process is realized in a compact area of 0.0056 mm <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sup> . Measurements show that the TDC achieves an 8.5-ps resolution and an 11-bit dynamic range (DR). Full range linearity measurement shows a maximum differential nonlinearity (DNL) of 0.3 LSB and integral nonlinearity (INL) of 2.3 LSB. The power consumption is only 0.198 mW at a 15-MS/s conversion rate, resulting in a favorable figure of merit (FoM) of 0.021 pJ/conversion step. The results show the effectiveness of the proposed TDC for improved linearity and resolution.

A Fast Lock All-Digital MDLL Using a Cyclic Vernier TDC for Burst-Mode Links

An all-digital multiplying delay-locked loop (MDLL)-based clock multiplier featuring a time-to-digital converter (TDC) to achieve fast power-on capability is presented. The proposed MDLL adopts a new offset-free cyclic Vernier TDC to achieve a fast lock time of 15 reference clock cycles while maintaining a wide detection range and high resolution. The proposed offset-free TDC also uses a correlated double sampling technique to remove mismatch and offset issues, resulting in low jitter characteristics. After the MDLL is quickly locked, the TDC is turned off, and it goes into delta-sigma modulator (DSM)-based sequential tracking mode to reduce power consumption and improve jitter performance. Implemented in a 65-nm 1.0-V CMOS process, the proposed MDLL occupies an active area of 0.043 mm2 and generates a 2.4-GHz output clock from a 75-MHz reference clock (multiplication factor N = 32). It achieves an effective peak-to-peak jitter of 9.4 ps and consumes 3.3 mW at 2.4 GHz.

Three-Step Cyclic Vernier TDC Using a Pulse-Shrinking Inverter-Assisted Residue Quantizer for Low-Complexity Resolution Enhancement

Herein, we present a cyclic Vernier time-to-digital converter (TDC) using a pulse-shrinking inverter-assisted residue quantizer (IRQ). Previous pulse-shrinking techniques suffer from a nonuniform shrink rate and time offset that slows the conversion and increases power consumption. The proposed pulse-shrinking IRQ reduces the time difference between residue signals instead of shrinking the pulse width. This approach achieves a high resolution with low power consumption and a high conversion rate. The critical tradeoff between resolution and dynamic range (DR) is addressed using a three-step cyclic conversion approach: coarse, fine, and residue quantization steps. The adverse effect of the oscillator startup time on linearity is analyzed, and a correction method is proposed using both on-chip circuit design and off-chip data processing. The proposed TDC is fabricated using a 180-nm CMOS process in a core area of 0.11 mm <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sup> . The TDC can be configured into one of four resolution modes, 36, 64, 89, and 135 ps, at conversion rates of 0.82, 1.29, 1.47, and 1.86 MS/s, respectively. A wide DR of up to 179 ns is achieved. The linearity is well performed with a maximum integral nonlinearity (INL)/differential nonlinearity (DNL) of 0.4/0.73 LSB at a conversion rate of 1.86 MS/s. An effective number of bits, N <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">linear</sub> up to 9.88-bit, and a figure-of-merit (FoM) down to 0.31 pJ/conversion are achieved by consuming 0.55 mW.

A High-Linearity Vernier Time-to-Digital Converter on FPGAs With Improved Resolution Using Bidirectional-Operating Vernier Delay Lines

Time-to-digital converters (TDCs) act as a core component in many timing-critical systems. Tapped delay line is the most widely used style for the field-programmable gate-array (FPGA)-based TDCs, but it suffers from several intractable problems such as poor nonlinearity and long delay-line occupation. Recently, a new ring-oscillator-based Vernier TDC circuit using carry chains was demonstrated to have much smaller nonlinearity with a much shorter delay line. Since the used delay line is not compensated, the timing jitter increases (or the precision degrades) remarkably when the oscillation number is large. This would incur undesirable lower resolution selection to maintain acceptable precision. In this article, a novel bidirectional-operating Vernier delay line structure is proposed to reduce the required oscillation number during the fine time measurement. Traditionally, for the Vernier delay line, the fast signal propagates along the slow delay line, while the slow signal propagates along the fast delay line, to which we call the normal Vernier delay line. The new structure proposes two parallelized Vernier delay line, consisting of one normal Vernier delay line and another abnormal Vernier delay line. The term “abnormal” refers to that the fast and slow signals are unusually fed to the fast and slow delay lines, respectively. A prototype TDC circuit based on this new method was implemented on a Stratix III FPGA. Test results demonstrate that by adopting the proposed novel circuit architecture, both the resolution and the root-mean-square error can be improved from the 30–40-ps level to the 20–30-ps level.

A 77-GHz Mixed-Mode FMCW Generator Based on a Vernier TDC With Dual Rising-Edge Fractional-Phase Detector

A 77-GHz frequency-modulated continuous-wave (FMCW) generator is presented for millimeter-wave (mm-wave) radar applications. The FMCW chirp is provided by a mixed-mode phase-locked loop (PLL). A dual rising-edge fractional-phase detector based on time-to-digital converter (TDC) is proposed to overcome the problem caused by the rising and falling time mismatch. A 2.3 ns detection range, 10 ps resolution Vernier TDC is employed in the detector to cover the two consecutive rising edges with less power consumption. A self-calibrated delay chain is employed in the Vernier TDC to overcome process, voltage and temperature (PVT) variations. Furthermore, sampling-edge selection technique is utilized to avoid the glitch during phase detection. A divider-less frequency error estimator is presented to save area and power. By employing a coarse-fine segmented digital-to-analog converter (DAC), the generator supports triangular and sawtooth-like FMCW chirp with reconfigurable period and bandwidth. An LC voltage- controlled oscillator (VCO) with split varactor is proposed to improve the linear tuning range. Implemented in 65 nm CMOS, the FMCW generator consumes 99 mW power and 0.7 mm $\times $ 0.8 mm chip area. The measurement results show that the phase noise from 78.7 GHz carrier is −87.4-dBc/Hz at 1 MHz offset. The measured root-mean-square (RMS) frequency error of a sawtooth-like FMCW chirp with 4 GHz bandwidth and 0.1 ms period is 205 kHz.

Analysis and Correction of Noise Injection Due to Parallel-Output-Misalignment (POM) Effects in Ring-Type Time-to-Digital Converters (TDCs)

A phenomenon called parallel-output misalignment (POM), which intrinsically occurs in ring-type time-to-digital converters (TDCs) like gated-ring oscillator (GRO) or Vernier-ring TDCs, is discussed in this paper. We found that the phase noise caused by POM error may be larger than that due to quantization error by up to 22 dB or even more. Thus, the overall phase noise contribution is dominated by the POM effect rather than the quantization error. This paper proposes a conjoined-ring Vernier (CRV) TDC with a POM error correction circuit that can eliminate the POM error and its consequent corruption on phase noise performance, making quantization error as being the only contribution of the overall phase noise. Meanwhile, the proposed TDC implementation maintains competitive performance in terms of fine time resolution (3 or 0.8 ps) and a flexible large time-length detection range (12 ns) capability in 40-nm CMOS technology. The CRV structure operates like a phase cutter, which separates the time interval into segments with an identical length of about 160 ps, except the residue segment ( $N$ -calibration circuit, is developed to correct the linearity.

Structure of All-Digital Frequency Synthesiser for IoT and IoV Applications

In recent years number of Internet of Things (IoT) services and devices is growing and Internet of Vehicles (IoV) technologies are emerging. Multiband transceiver with high performance frequency synthesisers should be used to support a multitude of existing and developing wireless standards. In this paper noise sources of an all-digital frequency synthesiser are discussed through s-domain model of frequency synthesisers, and the impact of noise induced by main blocks of synthesisers to the overall phase noise of frequency synthesisers is analysed. Requirements for time to digital converter (TDC), digitally controlled oscillator (DCO) and digital filter suitable for all-digital frequency synthesiser for IoT and IoV applications are defined. The structure of frequency synthesisers, which allows us to meet defined requirements, is presented. Its main parts are 2D Vernier TDC based on gated ring oscillators, which can achieve resolution close to 1 ps; multi core LC-tank DCO, whose tuning range is 4.3–5.4 GHz when two cores are used and phase noise is −116.4 dBc/Hz at 1 MHz offset from 5.44 GHz carrier; digital filter made of proportional and integral gain stages and additional infinite impulse response filter stages. Such a structure allows us to achieve a synthesiser’s in-band phase noise lower than −100 dBc/Hz, out-of-band phase noise equal to −134.0 dBc/Hz and allows us to set a synthesiser to type-I or type-II and change its order from first to sixth.

A 900-MHz, 3.5-mW, 8-bit Pipelined Subranging ADC Combining Flash ADC and TDC

In this paper, we propose a time-based analog-to-digital converter (ADC) architecture combining a flash ADC and vernier time-to-digital converter (TDC) to achieve both high speed and high resolution. The flash ADC and vernier TDC are pipelined to increase the conversion speed. A charge-steering amplifier is used for low-power residue transfer. A common level adjuster is added to the output stage of the charge-steering amplifier to stabilize the output common level against process, voltage, and temperature variation. Moreover, the vernier TDC using a dynamic delayer enables low-power operation. An 8-bit ADC test chip fabricated with 65-nm CMOS technology had a high sampling frequency (900 MHz) and low power consumption (3.5 mW). The figure of merit was 32 fJ/conversion step.

Low‐power, latch‐based multistage time‐to‐digital converter in 65 nm CMOS technology

SummaryIn this paper, a low‐power and high‐resolution latch‐based time‐to‐digital converter (TDC) based on a multistage scheme is proposed. The proposed multistage TDC includes coarse, middle, and fine stages. The coarse stage is a new design of the flash TDC that is implemented by latches without using the delay cell. Also, the middle stage is a new design of the Vernier TDC with employed latches. The fine stage comprises parallel latches with different input loads.

Low Power and Small Area, 6.9 ps RMS Time-to-Digital Converter for 3-D Digital SiPM

Time-of-flight measurements are becoming essential to the advancement of several fields, such as preclinical positron emission tomography and high energy physics. Recent developments in single photon avalanche diode (SPAD)-based detectors have spawned a great interest in digital silicon photomultipliers (dSiPMs). To overcome the tradeoff between the photosensitive area and the processing capabilities in current 2-D dSiPM, we propose a novel 3-D digital SiPM, where the SPAD, designed for maximal photosensitive area, will be stacked in 3-D over the electronic circuits, designed in a CMOS node technology. All readout circuits will be implemented directly under the SPAD real estate, including quenching circuit, time-to-digital converter (TDC) and digital readout electronics. This paper focusses on the TDC element of this system, designed in TSMC CMOS 65 nm. This ring oscillator-based Vernier TDC requires only 25 $ {\times }$ 50 $ {\mu }\text{m}^{2}$ and 160 $ {\mu }\text{W}$ , and achieves 6.9 ps rms timing accuracy.

Toward Implementing Multichannels, Ring-Oscillator-Based, Vernier Time-to-Digital Converter in FPGAs: Key Design Points and Construction Method

For TOF positron emission tomography (TOF PET) detectors, time-to-digital converters (TDCs) are essential to resolve the coincidence time of the photon pairs. Recently, an efficient TDC structure called ring-oscillator-based (RO-based) Vernier TDC using carry chains was reported by our team. The method is very promising due to its low linearity error and low resource cost. However, the implementation complexity is rather high especially when moving to multi-channels TDC designs, since this method calls for a manual intervention to the initial fitting results of the compilation software. In this paper, we elaborate the key points toward implementing high performance multi-channels TDCs of this kind while keeping the least implementation complexity. Furthermore, we propose an efficient fine time interpolator construction method called the period difference recording which only needs at most 31 adjustment trials to obtain a targeted TDC resolution. To validate the techniques proposed in this paper, we built a 32-channels TDC on a Stratix III FPGA chip and fully evaluated its performance. Code density tests show that the obtained resolution results lie in the range of (23 ps ~ 37 ps), the differential nonlinearity (DNL) results lie in the range of (-0.4 LSB ~ 0.4 LSB) and the integral nonlinearity (INL) results lie in the range of (-0.7 LSB ~ 0.7 LSB) for each of the 32 TDC channels. This paper greatly eases the designing difficulty of the carry chain RO-based TDCs and can significantly propel their development in practical use.

A 2.2-ps Two-Dimensional Gated-Vernier Time-to-Digital Converter With Digital Calibration

This brief presents a two-dimensional (2-D) Vernier time-to-digital converter (TDC) which uses two 3-stage gated ring oscillators (GROs) in the $X/Y$ Vernier branches. The already small Vernier quantization noise (∼10.6 ps) is improved by the first-order noise shaping of the GRO. Moreover, since all the delay differences between the $X$ and $Y$ phases can be used (rather than only the diagonal line of the one-dimensional architecture), the intrinsic large latency time of the Vernier architecture is dramatically reduced. The TDC is implemented in a 65-nm CMOS process and consumes 2.3 mA from 1.0 V. The measured total noise integrated over a bandwidth of 1.25 MHz yields an equivalent TDC resolution of 2.2 ps, whereas the average latency time (within 2 ns) is less than 1/6 of that in a standard Vernier TDC.

CMOS time‐to‐digital converters for mixed‐mode signal processing

This study provides an in-depth review of the principles, architectures and design techniques of CMOS time-to-digital converters (TDCs). The classification of TDCs is introduced. It is followed by the examination of the parameters quantifying the performance of TDCs. Sampling TDCs including direct-counter TDCs, tapped delay-line TDCs, pulse-shrinking delay-line TDCs, cyclic pulse-shrinking TDCs, direct-counter TDCs with interpolation, vernier TDCs, flash TDCs, successive approximation TDCs and pipelined TDCs are studied and their pros and cons are compared. Noise-shaping TDCs that reduce in-band noise below technology limit are investigated. These TDCs include gated ring oscillator TDCs, switched ring oscillator TDCs, relaxation oscillator TDCs, ΔΣ TDCs and MASH TDCs. The performance of sampling and noise-shaping TDCs is compared. The direction of future research on TDCs is explored.

A 2-D GRO Vernier time-to-digital converter with large input range and small latency

The proposed time-to-digital converter (TDC) arranges two Vernier gated-ring-oscillator (GRO) branches in a 2-dimension (2-D) fashion. All delay differences between X phases and Y phases can be used, rather than only the diagonal line. The large latency time inherited from Vernier structure is therefore dramatically reduced. The TDC is implemented in a 90nm CMOS process and consumes 1.8mA from 1.2V. The measured input range can safely cover a full period of a 50MHz sampling signal. With the same delay elements, the latency time is less than 1/6 of that needed in a standard Vernier TDC.

A High Resolution First Order Noise-Shaping Vernier Time-to-Digital Converter

In this paper, we propose a noise reduction method for a Vernier Time-to-Digital Converter (VTDC) using a first-order noise shaping structure and a gated ring oscillator (GRO). An 11bit VTDC with 4 p s effective resolution was designed and developed for a high performance All Digital Frequency Synthesizer (ADFS). The VTDC realized in 180nm CMOS, its power consumption depending on the time difference between input edges; 1 to 11mA from a 1.5 V supply.

A 3.6 mW, 90 nm CMOS Gated-Vernier Time-to-Digital Converter With an Equivalent Resolution of 3.2 ps

Two gated ring oscillators (GROs) act as the delay lines in an improved Vernier time-to-digital converter (TDC), where the already small quantization noise of the standard Vernier TDC is further first-order shaped by the GRO operation. The TDC has been implemented in a 90 nm CMOS process and consumes 3 mA from 1.2 V when operating at 25 MHz. The native Vernier resolution of the TDC is 5.8 ps, while the total noise integrated over a bandwidth of 800 kHz yields an equivalent TDC resolution of 3.2 ps.

A Cyclic Vernier TDC for ADPLLs Synthesized From a Standard Cell Library

This paper presents a cyclic Vernier time-to-digital converter (TDC) with digitally controlled oscillators (DCOs), targeted for a synthesizable all-digital phase locked loop (ADPLL). All functional blocks in the TDC are implemented with digital standard cells and placed-and-routed (PR thus, the TDC is portable and scalable to other process technologies. The effect of P&R mismatch is characterized in calibration mode, and utilized to achieve a minimum TDC resolution of 5.5 ps. The TDC was fabricated in a 65 nm CMOS process, and occupies 0.006 mm2.

Single-Stage Vernier Time-to-Digital Converter with Sub-Gate Delay Time Resolution

This paperpresents a single-stage Vernier Time-to-Digital Converter (VTDC) that utilizes the dynamic-logic phase detector. The zero dead-zone characteristic of this phase detector allows for the single-stage VTDC to deliver sub-gate delay time resolution. The single-stage VTDC has been designed in 0.13μm CMOS technology. The simulation results demonstrate a linear input-output characteristic for input dynamic range from 0 to 1.6ns with a time resolution of 25ps.

Two-Dimensions Vernier Time-to-Digital Converter

A two-dimensions Vernier algorithm applied to a time to digital converter (TDC) is presented. The solution proposed minimizes the length of the delay lines used to perform the digital conversion leading to a better efficiency compared to traditional linear approaches. A 7-bits TDC prototype, targeted for all digital PLL application, was realized in 65 nm CMOS technology with a time resolution of 4.8 ps and a power consumption of 1.65 mW for a conversion rate of 50 Msps. The longest delay line used in such a prototype is one third than what would have been required for a standard Vernier TDC.