Vedic Multiplier Research Articles

Implementation of Fast Convolution using Robust Vedic Multiplier of Radix-2

Convolution is an algorithm which is mainly used in video, audio and image processing. Convolution calculation is simple in steps however it consumes a lot of memory as well as power in the computational process. It is a mathematical algorithm which is also used in the applications like filtering, edge detection, de-noising, compression etc., as it can be exploit computational power. In this paper, we implemented the speed of discrete linear convolution using robust Vedic multiplier which is one of the fastest multipliers with two finite-length sequences. By implementing convolution with Vedic multiplier power, area and delay are reduced. This implementation process can be realized by simplifying the convolution building block.

Design of High-Speed Multiplier Architecture Based on Vedic Mathematics

High speed and efficient multipliers are essential components in today’s computational circuits like digital signal processing, algorithms for cryptography and high performance processors. Invariably, almost all processing units will contain hardware multipliers based on some algorithm that fits the application requirement. Tremendous advances in VLSI technology over the past several years resulted in an increased need for high speed multipliers and compelled the designers to go for trade-offs among speed, power consumption and area. Amongst various methods of multiplication, Vedic multipliers are gaining ground due to their expected improvement in performance. A novel multiplier design for high speed VLSI applications using Urdhva-Tiryagbhyamsutra of Vedic Multiplication has been presented in this paper. The multiplier architecture is implemented using Verilog coding and synthesise during Cadence RTL Compiler. Physical design is implemented using Cadence Encounter RTL-to-GDSII System using standard 180nm technology. The proposed multiplier architecture is compared with the conventional multiplier and the results show significant improvement in speed and power dissipation.

Implementation of high speed and area efficient MAC unit for industrial applications

In today’s digital processors the everlasting demand is the enhancement of knack in processors to handle the complexities resulted in the incorporation of some of the processor cores in a single chip. Then more the load on the processor is not fewer in the primary system. This load can be minimized by augmenting the central processor with the co-processors, which are made up to work with a particular type of functions like graphics, signal processing, numeric computation, etc. Hence, in which the multiplier and accumulator (MAC) unit is most leading co-processor and toil as the heart of the digital signal processors. Faster processes are of great significance in MAC unit. Ultimate digital signal processing algorithms depend significantly on multiply and accumulator (MAC) performance. Hence after a deep study and investigation, we found that the proficiency of Urdhva-tiryagbhyam Vedic multiplication algorithm found to be superior in comparison with other conventional multipliers. The rapidity of multiplication and addition governs the execution speed and performance of entire setup. Here we will design and analyze the performance of MAC unit, and thus, the delay and area parameters are optimized using various multipliers such as Array, Wallace, Vedic multipliers, etc. The proposed method is designed using Xilinx 12.3 and tested using the Virtex5-XC5VLX110T device.

Review on FPGA Implementation of 1616 Vedic Multiplier in VHDL Environment

Review on FPGA Implementation of 1616 Vedic Multiplier in VHDL Environment

Analysis of Area and Delay for Floating Point Matrix Multiplication

In this paper, a new area and delay minimization architecture is proposed for rank-1 update matrix–matrix multiplication whose inputs are double precision floating point number. The architecture design is based on pipelined multiplication which handles matrix of arbitrary sizes; the processing data are stored in dedicated on-chip BRAM. This minimization is introduced to designers as a trade-off between bandwidth and local memory. Analysis is presented for the design parameters optimal choice. In addition, Vedic matrix multiplication architecture is given in order to explore the variations in power, delay and memory. The hardware architecture is described in Verilog HDL synthesized for a family virtex-6 and device xc6vlx240t FPGA, which scale more than 40 processing elements. Various parameters like LUTs, Slices, bonded IOBs, frequency, DSP48E1S, delay, Power, CPU Completion time and Memory usage are analysed. Rank 1 update consumes a power of 2.520 watt and has a delay of 5.277 ns respectively. Comparing other rank-1 multiplication methods our proposed algorithms uses 15% less area resources and improves the delay in 12%.

Design of the 16-bit Vedic Multiplier Based on Compressor Adder

Design of the 16-bit Vedic Multiplier Based on Compressor Adder

Design and Implementation of Vedic Multipliers Using Reversible Logic Gates

Implementing the already existing circuits or new circuits using reversible logic has drawn a significant interest in recent years as a promising computing technique having application in low power CMOS, quantum computing, nanotechnology, optical computing …etc. Reversible logic gates offer significant advantages such as high speed, low power, ease of fabrication …etc. Also, circuits designed using these circuits would have better performance as compared to existing circuits. Main goals of reversible logic synthesis are to minimize the garbage, to minimize the delay, to minimize the total number of gates, to minimize the width of the circuit. In this paper, designer implemented 2 × 2 and 4 × 4 bit Vedic multipliers using reversible logic gate.

Efficient Realization of Vinculum Vedic BCD Multipliers for High Speed Applications

Decimal multipliers play an important role in our day to day life for commercial, financial and tax applications. Every processor multiplier acts as the basic building block which decides the performance of processor. Time and again research is going on to design high-performance, low-latency BCD multiplier architectures. This paper proposes a new approach to BCD multiplication using vinculum number system. The key feature of the proposed architecture uses entirely a new one digit ROM based BCD multiplier that uses vinculum numbers as operands. Using this one digit BCD multiplier, an N digit BCD multiplier is built by using the vedic vertical cross wire method (Urdhav Triyagbhyam). We have also used our proposed multi operand VBCD Adder (Vinculum BCD Adder) [my paper 26] to add the partial products. In this paper, we show that this approach is a promising alternative to conventional BCD multiplication or other decimal multiplication methods that use alternative decimal representations like 5211, 4221, Xs3 etc.

Bit wise and delay of vedic multiplier

The Vedic multiplier is derived from the ancient mathematics called Vedic mathematics .The ancient mathematics has different sutras in that we use Urdhva Tiryagbhyam sutra which means clock wise and vertically . As we know that binary multiplication is not possible so that instead we use binary addition or subtraction instead of it. The key process for the multiplication is the speed of the processor. The fastest mode of multiplication is the Vedic multiplier. In this paper we want to show the delay and utilization of components available for the multiplier by executing the code. The comparison of delay from some papers was also proposed in this paper. The research is going on the Vedic mathematics to overcome the problems on the conventional mathematics. In future Vedic multiplier plays an important role in the DSP (Digital Signal Processing).As it is the fastest and efficient mode of operation. In this paper I am calculating the bit wise delay up to 32-bit. The whole analysis was done in Xilinx. The ISM wave forms for every bit up to 32-bit was to be obtained. The utilization, used, available, utilized analysis was also taken. The whole process was done in XILINX software.

New Technique Based Peasant Multiplication for Effcient Signal Processing Applications

<p class="Standard"><span lang="EN-IN">The Direct Form FIR channel is utilized for DSP application where the channel request is settled. For the most part this channel devours more range and power. To defeat this issue Multiplier Control Signal Decision window (MCSD) plans is joined into Direct Form FIR channel to powerfully change the channel arrange. MCSD structures comprise of Control flag Generator (CG) and Amplitude Detection (AD) rationale circuits. Advertisement rationale is utilized to disavow the correct duplication process and screen the amplitudes of information tests. CG is utilized to control the channel operation through inside counter. Traditional reconfigurable FIR channel is planned utilizing Vedic Multiplier that devours more territory and deferral. In this paper, changed reconfigurable FIR filer is intended to additionally decrease the APT (Area, Power and Timing) item. The proposed Reconfigurable FIR filer, Vedic Multiplier is supplanted by Russian Peasant Multiplication procedure. Subsequently adjusted Reconfigurable FIR channel with Russian Peasant Multiplier expends less region, postponement and power than all analyzed techniques.</span></p>

An efficient design of Vedic multiplier using ripple carry adder in Quantum-dot Cellular Automata

Quantum-dot Cellular Automata (QCA) is one of the emerging nanotechnologies, which yields attractive features like high speed, low power consumption and smaller size for implementing computing architecture in contrast to the CMOS technology. Numerous studies of adders and multiplier have been reported in this direction using QCA. This paper mainly focuses on designing of 8 × 8 Vedic multiplier in QCA using Urdhva Tiryagbhyam sutra. An efficient structure of 4-bit Vedic multiplier is used to construct an 8-bit multiplier. Moreover, the additions of generated partial products are realized using ripple carry adders and full adders. A generalized structure of N × N Vedic multiplier and the complexity of N × N multiplier design is also discussed. All the designs are simulated on QCADesigner tool and it confirms the efficiency of the proposed design. The simulation results show that the proposed design of 8 × 8 Vedic multiplier has reduced 60% cell count, 78% area, and 75% delay as compared to the 8 × 8 Wallace multiplier. In addition, it achieves equal complexity in term of cell count, but delay and area are reduced by 64% and 18% respectively compared to Array I multiplier. Furthermore, a general expression for the number of majority gates, inverters, crossovers, and delay is derived and compared with the Array I and Array II multiplier.

Register Pre-Allocation based Folded Discrete Tchebichef Transformation Technique for Image Compression

Recently, the large size data, power and real-time processing abilities are major issues in Digital Signal Processing/multimedia applications which require an adaptable architecture. The tool used for computing data decorrelation in the image processing applications refers Discrete Tchebichef Transform (DTT) which offers better performance than the DCT due to its bitstream coding capabilities. This paper proposes a novel model of Discrete Tchebichef Transform (DTT) architecture with Register Pre-allocation based Folded Architecture (RPFA) for image compression. Through the cross-connection of folded architecture, the number of register usage is reduced. A Partial Cross Split Vedic Multiplier (PCSVM) method is introduced in the proposed DTT architecture. This multiplier design involves the cross function of the Vedic multiplier with the split pattern of multiplication binary stream. The optimal design of DTT architecture yields a minimum amount of FlipFlop (FF) counts, a latency and power consumption. The proposed PCSVM achieves higher Peak Signal to Noise Ratio (PSNR), better Structural Similarity Index (SSIM), lower delay, area, power consumption, Power-Delay Product (PDP), Mean Square Error (MSE) than the existing multiplier architectures. The proposed RPF-DTT architecture achieves a significant reduction in the resource consumption than the exact and approximate DTT architectures.

Different I/O Standard and Technology Based Thermal Aware Energy Efficient Vedic Multiplier Design for Green Wireless Communication on FPGA

This paper deals with low power multiplier design that plays a significant role in green wireless communications systems. Over the period of time, researchers have proposed various multiplier designs in order to get high speed. Vedic multiplier is considered as one of the low power multiplier along with high speed as compared with traditional array and booth multipliers. Vedic Multiplier contains a total of sixteen algorithms/sutras for predominantly logical operations. This research focuses on thermal aspects and energy efficiency of wireless communications systems with the thermal aware low power design of Vedic Multiplier. Temperature plays an important role on the performance of any device. The primary purpose of this research is to enhance the thermal stability of the wireless communications. Energy efficient IO standards are used to decrease the power dissipation of Vedic Multiplier and that eventually decrease power dissipation of wireless communications systems. In order to study the effect of different process technology (40, 65, 90 nm) on our design, a novel design is implemented on 40, 65 and 90 nm based FPGA. In this work, we are integrating thermal aware design approach for energy efficient Vedic Multiplier on various FPGA using LVCMOS and HSTL I/O standard. LVCMOS is an acronym for Low Voltage Complementary Metal Oxide Semiconductor and HSTL is an acronym for High Speed Transceiver Logic. In this Vedic Multiplier, we are using three LVCMOS I/O standard and nine HSTL I/O standard. In order to test the thermal sustainability of our Vedic Multiplier design, we are testing it in three different room temperatures i.e. 20, 30, and 40 °C. Using LVCMOS25, there is 12.99, 19.23 and 10.28% reduction in power dissipation on 90, 65 and 40 nm FPGAs respectively. For LVCMOS25, when our Vedic Multiplier design is migrated from 40 nm design to 90 nm FPGA design, there is 87.72% reduction in power dissipation of Vedic Multiplier when temperature is kept constant at 20 °C. When temperature is scaled down from 50 to 20 °C there is 12.45, 14.93, 12.84, 9.45 and 8.48% saving in power dissipation on using HSTL_I, HSTL_I_12, HSTL_I_18, HSTL_I_DCI and HSTL_I_DCI_18 IO Standard respectively on 90 nm FPGA.

Design of 16 Bit Vedic Multiplier Using Semi-Custom and Full Custom Approach

Design of 16 Bit Vedic Multiplier Using Semi-Custom and Full Custom Approach

Modified Vedic Multipliers: A Review

Modified Vedic Multipliers: A Review

Vedic Multiplier Using Efficient Compressor to Reduce Delay for Vedic Multiplier : A Review

Vedic Multiplier Using Efficient Compressor to Reduce Delay for Vedic Multiplier : A Review

Design and FPGA Implementation of 4x4 Vedic Multiplier using Different Architectures

Design and FPGA Implementation of 4x4 Vedic Multiplier using Different Architectures

Design of Vedic Multiplier Using SQRT Carry Select Adder (CSLA)

Vedic multiplier is designed using area-efficient Carry Select Adder (CSLA). As the multiplication is the process of subsequent addition, adder is important block in implementation of multiplier. Digital adder has problem of carry propagation, thus carry select adder is used instead of simple Ripple Carry Adder (RCA). Carry select adder is known to be one of the fastest adder structures. Here Vedic multiplier is implemented instead of normal multipliers like add and shift multiplier, array multiplier etc. The goal is to design Vedic multiplier based on crosswise and vertical algorithms using area efficient Sqrt CSLA. Conventional CSLA designs like Binary to Excess one Converter (BEC) based CSLA and Modified CSLA (MCSLA) are compared with proposed CSLA design to prove its efficiency. It shows improved performance in terms of area. This renovated CSLA is used to design proposed Vedic multiplier. The proposed Sqrt CSLA based Vedic multiplier provides better results in power and speed of the digital circuits.

Design and Implementation of High Speed and Area Efficient MAC Unit

The Multiply-Accumulate unit is the main computational kernel in Digital Signal Processing application. To determine the speed of the entire hardware systems, the Multiply and Accumulate Unit (MAC) always play an important role. The efficient MAC Unit is used to support the variable precisions and parallel functions with high desirability. In this work, 64 Bit MAC Design using area efficient Vedic Multiplier and Square Root Carry-Select Adder (SQRT CSLA) for DSP Processors is implemented. To design a N*N Vedic MAC Design, four N/2*N/2 Vedic Multiplier and Square Root Carry Select Adder are required for an efficient design. Various adders such as Ripple Carry Adder, Carry Save Adder, Square root Carry Select Adder and multipliers such as Booth Multiplier, Wallace Tree Multiplier and Vedic Multiplier are analyzed. Conventional MAC design is implemented using Vedic Multiplier with Ripple Carry Adder (RCA). To reduce the Look-Up Tables (LUTs), Delay and Power, the Vedic Multiplier with Square Root Carry Select Adder (SQRT CSLA) is proposed in this work. The Conventional and Proposed MAC design are coded in Verilog HDL Language, synthesized using Xilinx ISE and simulated using Modelsim XE. Number of LUT Counts, Delay and Power of the conventional MAC and Proposed MAC are compared.

Design and Implementation of High Speed Vedic Multiplier in SPARTAN 3 FPGA Device

Digital systems which are more effective are necessary due to the enormous growth in the technology. So, we go for multipliers which are playing a key role in each and every digital domain device. Also, designing a multiplier with high speeds to perform ALU operations is an important aspect in digital signal processing. These operations are used for DFT, convolution etc. Hence, professionals in DSP domain are trying to develop innovative algorithms and hardware implementation. It is very essential to employ a multiplier which is more effective. They are many standard algorithms that are existing to reduce the area and time needed for execution. Vedic era described algorithms in vedic mathematics that supply an efficiency which are of high level. They provide 16 sutras for the operation of multiplication. Here, we discuss about urdhva tiryakbhyam algorithm for multiplication operation. Therefore, vedic algoritm provides better efficiency in comparison to that of conventional multipliers.