Abstract: Now a days security is the prime part for both, the satellites communication of the electronics data and the stored data, hence encryption is important for information processing system and communication network. The proposed approach is easy to learn due the use of speed efficient Vedic multiplier. Since it minimizes the execution time and area, so the delay and power consumption is further decrease by the compact and flexible approach in the Mix column transform which takes different approach rather than conventional multiplication previously. The structure style of modeling helps to easy understandable the proposed design of algorithm. BFV is the symmetrical has designed and verified in the Verilog HDL in Xilinx tool. In this project we present using kogge-stone adder and Vedic multiplier.