Vector Register Research Articles

Vector register design for polycyclic vector scheduling

Vector register design for polycyclic vector scheduling

Vector register design for polycyclic vector scheduling

Vector register design for polycyclic vector scheduling

Vector register design for polycyclic vector scheduling

Vector register design for polycyclic vector scheduling

Complexity of optimal vector code generation

Computers with multiple functional units allow a set of instructions to execute concurrently. An optimizing compiler for these computers needs to schedule its generated scalar and vector code to maximize the runtime performance by minimizing the machine's idle time. Chimes are used to measure the computational length (cpu time) of the generated vector code of a given vector expression tree. This paper shows how to calculate the minimum number of chimes of the optimal vector code for a vector expression tree. We prove that a code generation algorithm which generates optimal code is computationally intractable, even when generating code for a machine with an infinite number of vector registers. This result indicates that heuristic approaches to the code generation problems are needed.

Vector processing approach to constrained network problems

Modification of algorithms designed for scalar computing, to take advantage of vector processing, raises several challenges. This article presents the vectorization of the primal simplex based network algorithm and results in a 50% improvement in computational time. One of the major contributors to this improvement is the matching of the size of the pricing candidate list to the vector register size. The side constraints are relaxed into a single surrogate constraint. The single constraint network algorithm is vectorized and used as the basis for solving large-scale constrained network problems. Computational experiments are presented which illustrate the vectorization of the network code as well as the ability of the surrogate constraint approach to deal with large constrained network problems.

Parallel variable-band Choleski solvers for computational structural analysis applications on vector multiprocessor supercomputers

A Choleski method used to solve linear systems of equations that arise in large scale structural analyses is described. The method uses a novel variable-band stroage scheme and is structured to exploit fast local memory caches while minimizing data access delays between main memory and vector registers. Several parallel implementations of this method are described for the CRAY-2 and CRAY Y-MP computers demonstrating the use of microtasking and autotasking directives. A portable parallel language, FORCE, is also used for two different parallel implementations, demonstrating the use of CRAY macrotasking. Results are presented comparing the matrix factorization times for three representative structural analysis problems from runs made in both dedicated and multi-user modes on both the CRAY-2 and CRAY Y-MP computers. CPU and wall clock timings are given for the various parallel methods and are compared to single processor timings of the same algorithm. Computation rates over 1 GIGAFLOP (1 billion floating point operations per second) on a four processor CRAY-2 and over 2 GIGAFLOPS on an eight processor CRAY Y-MP are demonstrated as measured by wall clock time in a dedicated environment. Reduced wall clock times for the parallel methods relative to the single processor implementation of the same Choleski algorithm are also demonstrated for runs made in multi-user mode.

COMPILER TECHNIQUES FOR OPTIMIZING MEMORY AND REGISTER USAGE ON THE CRAY 2

In a previous work [3], a cyclic scheduling method was shown efficient to generate vector code for the Cray-2 architecture, and compared to existing compilers. This method was using the framework of microcode compaction through a simplified model of the Cray-2 vector instruction stream. In this paper, we further elaborate on two issues: how to model the machine architecture within the underlying cyclic scheduling method, and the performance of the register allocation technique that must endeavour to make a good use of the scarce resource represented by vector registers. Comparisons with other related work in the area of RISC and VLIW processors are presented as well as performance data.

A unified vector/scalar floating-point architecture

In this paper we present a unified approach to vector and scalar computation, using a single register file for both scalar operands and vector elements. The goal of this architecture is to yield improved scalar performance while broadening the range of vectorizable applications. For example, reduction operations and recurrences can be expressed in vector form in this architecture. This approach results in greater overall performance for most applications than does the approach of emphasizing peak vector performance. The hardware required to support the enhanced vector capability is insignificant, but allows the execution of two operations per cycle for vectorized code. Moreover, the size of the unified vector/scalar register file required for peak performance is an order of magnitude smaller than traditional vector register files, allowing efficient on-chip VLSI implementation. The results of simulations of the Livermore Loops and Linpack using this architecture are presented.

Programming in VS Fortran on the IBM 3090 for maximum vector performance

Programming techniques necessary for high performance on the 3090 Vector Facilities are illustrated, showing that VS Fortran programs can achieve near-maximum execution rates. Relevant features of the 3090 architecture are reviewed, stressing the need to make efficient use of a hierarchical storage system and take advantage of the compound vector instructions. The key programming techniques for managing the storage hierarchy are loop sectioning, loop distribution, and data compaction. Vector register, cache reuse, and virtual memory, storage format, and page reuse are shown to lead to efficient use of the vector registers, the high speed cache, and the virtual memory system, respectively. The multiply-and-add compound instruction is discussed.< <ETX xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">&gt;</ETX>

Magnetic observations at Georg von Neumayer station, Antarctica

In 1981 a German permanent wintering-over base — the Georg von Neumayer station (GVN) — was established. Since then, geophysical and meteorological parameters have been recorded continuously. Although it seems that an antarctic ice shelf is not suited as base for a permanent geophysical observatory, it could be shown, that the continous registration of the geomagnetic field vector at GVN is very useful for studies of ionospheric and magnetospheric phenomena. In order to separate true time variations of the geomagnetic data from local disturbances at first many careful statistical studies of the measured time series were necessary. For instance contaminating swell-effects could be detected, and it is important to distinguish these from geomagnetic pulsations.

Packaging Technology for the NEC SX Supercomputer

Technological considerations in realizing high-speed supercomputers are presented, focusing on large-scale integrated (LSI) chips, new circuit packaging technology, and a liquid cooling system. The Model SX-1 and SX-2 supercomputers employ a new circuit packaging technology achieving up to 1300 megaflops processing speeds with a 6-ns machine cycle. This new technology features a 1000-gate current mode logic (CML) LSI with 250 ps gate delay as a logic element, a I k bit bipolar memory with 3.5 ns access time for cache memory and vector registers, a 10 cm² multilayer ceramic substrate with thin film fine lines (25- \mu m width, 75- \mu m center-to-center), and a multichip package which contains up to 36 000 logic gates. A liquid cooling module is implemented for highdensity high-efficiency heat-conductive packaging for the arithmetic processor, in addition, high-density high-speed packaging of 64 kbit static metal-oxide semiconductor (MOS) RAM's are used to implement large-capacity fast main memory.