Vector Extensions Research Articles

Extending the NOEL-V Platform with a RISC-V Vector Processor for Space Applications

This paper describes the work carried out to extend the NOEL-V platform to include data-level parallelism (DLP) by implementing an integer subset of the RISC-V Vector Extension. The performance and resource utilization efficiency of the resulting vector processor for different levels of DLP (i.e., number of lanes) have been compared to the baseline scalar processor on a Xilinx Kintex Ultrascale field-programmable gate array, employing typical kernels for compute-intensive applications. The role of the memory subsystem has also been investigated, comparing the results obtained with a low-latency and a high-latency main memory. The results show that the speed-up due to the use of the vector pipeline increases with the number of lanes in the vector processor, achieving up to 23.0× the performance of the scalar processor with only 4.3× the resources of the baseline scalar processor. Using an implementation with 32 lanes increases performance even for problem sizes larger than the number of lanes, achieving up to more than 11.7× the performance of the scalar processor with just 1.9× its resource utilization for matrix multiplications. This work proves that implementations of the selected subset are easily scalable and fit for small-processor implementations in highly constrained space embedded systems.

Real-time processing approaches for interactive room acoustic auralization in the rtSOFE

Room acoustic simulation of early reflections with the mirror-image method for arbitrary room geometries is an exponential problem, which, if computed to a high reflection order, will quickly exceed available computational and memory resources. The real-time Simulated Open Field Environment (rtSOFE) is freely available room-acoustic simulation and auralization software based on the mirror-image method. For auralization, rtSOFE synthesizes room impulse responses for each playback channel from the list of mirror images. A convolver program receives these seconds-long room impulse responses and convolves them for each sound source, sums across sources, and performs the playback equalization. Both programs perform computations in multiple threads in parallel using the OpenMP library. Many operations are implemented with Intel Advanced Vector Extensions (AVX) to increase processing speed. Image source trees are terminated after a definable number of invisible parent sources, keeping the number of computed mirrors manageable. With this, rtSOFE is capable of computing room impulse responses to high reflection orders in interactive real-time settings. I will present the software concept and discuss the approaches that speed up the computation.

Vitruvius+: An Area-Efficient RISC-V Decoupled Vector Coprocessor for High Performance Computing Applications

The maturity level of RISC-V and the availability of domain-specific instruction set extensions, like vector processing, make RISC-V a good candidate for supporting the integration of specialized hardware in processor cores for the High Performance Computing (HPC) application domain. In this article, 1 we present Vitruvius+, the vector processing acceleration engine that represents the core of vector instruction execution in the HPC challenge that comes within the EuroHPC initiative. It implements the RISC-V vector extension (RVV) 0.7.1 and can be easily connected to a scalar core using the Open Vector Interface standard. Vitruvius+ natively supports long vectors: 256 double precision floating-point elements in a single vector register. It is composed of a set of identical vector pipelines (lanes), each containing a slice of the Vector Register File and functional units (one integer, one floating point). The vector instruction execution scheme is hybrid in-order/out-of-order and is supported by register renaming and arithmetic/memory instruction decoupling. On a stand-alone synthesis, Vitruvius+ reaches a maximum frequency of 1.4 GHz in typical conditions (TT/0.80V/25°C) using GlobalFoundries 22FDX FD-SOI. The silicon implementation has a total area of 1.3 mm 2 and maximum estimated power of ∼920 mW for one instance of Vitruvius+ equipped with eight vector lanes.

Vector Extensions in COTS Processors to Increase Guaranteed Performance in Real-Time Systems

The need for increased application performance in high-integrity systems such as those in avionics is on the rise as software continues to implement more complex functionalities. The prevalent computing solution for future high-integrity embedded products is multi-processor systems-on-chip (MPSoC) processors. MPSoCs include central processing unit (CPU) multicores that enable improving performance via thread-level parallelism. MPSoCs also include generic accelerators (graphics processing units [GPUs]) and application-specific accelerators. However, the data processing approach (DPA) required to exploit each of these underlying parallel hardware blocks carries several open challenges to enable the safe deployment in high-integrity domains. The main challenges include the qualification of its associated runtime system and the difficulties in analyzing programs deploying the DPA with out-of-the-box timing analysis and code coverage tools. In this work, we perform a thorough analysis of vector extensions (VExts) in current commercial off-the-shelf (COTS) processors for high-integrity systems. We show that VExts prevent many of the challenges arising with parallel programming models and GPUs. Unlike other DPAs, VExts require no runtime support, prevent design race conditions that might arise with parallel programming models, and have minimum impact on the software ecosystem, enabling the use of existing code coverage and timing analysis tools. We develop vectorized versions of neural network kernels and show that the NVIDIA Xavier VExts provide a reasonable increase in guaranteed application performance of up to 2.7x. Our analysis contends that VExts are the DPA approach with arguably the fastest path for adoption in high-integrity systems.

HPCG on long-vector architectures: Evaluation and optimization on NEC SX-Aurora and RISC-V

Accelerators are becoming a key component to improve efficiency in High-Performance Computing systems (HPC). While GPU based systems are widely used to accelerate HPC workloads, new systems based on long-vector architectures are rapidly gaining popularity. The development of optimized math libraries becomes fundamental to achieve high performance in those emerging vector architectures. This paper focuses on the optimization of the HPCG benchmark, which comprises four fundamental kernels found in many numerical applications. We target two relevant long-vector architectures like the NEC Vector Engine and the RISC-V ’V’ vector extension. Compared to the well-tuned proprietary solution, our open HPCG implementation achieves a 1.6% improvement in performance on the NEC Vector Engine and achieves near maximum memory bandwidth utilization in the two evaluated RISC-V vector accelerator designs.

FAUST: Design and implementation of a pipelined RISC-V vector floating-point unit

In this paper, we present Faust, a pipelined FPU for vector processing-capable RISC-V core developed within the European Processor Initiative (EPI) project. Faust is based on the open-source multi-format floating-point architecture FPnew that was extended and redesigned to support the RISC-V Vector extension specification (RVV) 1.0 and the most recent IEEE 754-2019 FP standard. Faust is extensively tested, mature and configurable, enabling ease of integration, as will be demonstrated in the paper. Faust can produce two binary32 operations or one binary64 operation per clock cycle. We have also developed FPU-V, an update of the SoftFloat-based reference model as a critical part of the UVM-based universal and extensible FPU verification environment. Faust was integrated and taped out as part of Vitruvius, a RISC-V Vector Processing unit of the EPAC1.0, the first EPI Accelerator Test Chip in GlobalFoundries 22FDX technology, and was shown fully operational at a target frequency of 1 GHz.

Acceleration of Particle Swarm Optimization with AVX Instructions

Parallel implementations of algorithms are usually compared with single-core CPU performance. The advantage of multicore vector processors decreases the performance gap between GPU and CPU computation, as shown in many recent pieces of research. With the AVX-512 instruction set, there will be another performance boost for CPU computations. The availability of parallel code running on CPUs made them much easier and more accessible than GPUs. This article compares the performances of parallel implementations of the particle swarm optimization algorithm. The code was written in C++, and we used various techniques to obtain parallel execution through Advanced Vector Extensions. We present the performance on various benchmark functions and different problem configurations. The article describes and compares the performance boost gained from parallel execution on CPU, along with advantages and disadvantages of parallelization techniques.

Accelerating Falcon Post-Quantum Digital Signature Algorithm on Graphic Processing Units

Since 2016, the National Institute of Standards and Technology (NIST) has been performing a competition to standardize post-quantum cryptography (PQC). Although Falcon has been selected in the competition as one of the standard PQC algorithms because of its advantages in short key and signature sizes, its performance overhead is larger than that of other lattice-based cryptosystems. This study presents multiple methodologies to accelerate the performance of Falcon using graphics processing units (GPUs) for server-side use. Direct GPU porting significantly degrades performance because the Falcon reference codes require recursive functions in its sampling process. Thus, an iterative sampling approach for efficient parallel processing is presented. In this study, the Falcon software applied a fine-grained execution model and reported the optimal number of threads in a thread block. Moreover, the polynomial multiplication performance was optimized by parallelizing the number-theoretic transform (NTT)-based polynomial multiplication and the fast Fourier transform (FFT)-based multiplication. Furthermore, dummy-based parallel execution methods have been introduced to handle the thread divergence effects. The presented Falcon software on RTX 3090 NVIDA GPU based on the proposed methods with Falcon-512 and Falcon-1024 parameters outperform at 35.14, 28.84, and 34.64 times and 33.31, 27.45, and 34.40 times, respectively, better than the central processing unit (CPU) reference implementation using Advanced Vector Extensions 2 (AVX2) instructions on a Ryzen 9 5900X running at 3.7 GHz in key generation, signing, and verification, respectively. Therefore, the proposed Falcon software can be used in servers managing multiple concurrent clients for efficient certificate verification and be used as an outsourced key generation and signature generation server for Signature as a Service (SaS).

Fast Multiple-Precision Integer Division Using Intel AVX-512

This paper reports on the implementation of a large integer division method that uses Intel Advanced Vector Extensions 512 (AVX-512), which is a 512-bit Single Instruction Multiple Data (SIMD) instruction set, and proposes a modification to a conventional division algorithm that makes it more SIMD instruction-friendly. More specifically, we use the Integer Fused Multiply-Add AVX-512 (AVX-512IFMA) subset, which is an instruction set that works well with large integer multiplication, to compute large integer divisions via a multiplication-based approach with a reciprocal. For the division process, we apply the most basic algorithm and divide-and-conquer methods and then use several techniques to compute efficiently with SIMD instructions in our implementation. We then combine these techniques and methods to implement our division function so that it can flexibly handle various sizes. To evaluate the performance of our proposed implementation, we executed our division program and the GNU Multiple Precision Arithmetic Library (GMP) on a Cannon Lake microarchitecture processor. A comparison of the execution times for our division program and GMP with various sizes showed that our method resulted in performance improvements of 25% to 35% on average, thus indicating that SIMD instructions are effective for fast arbitrary precision integer divisions.

AVX512Crypto: Parallel Implementations of Korean Block Ciphers Using AVX-512

Cryptographic algorithms are widely used as the foundation of various security systems and applications (e.g., secure communication, blockchain systems, and cloud services). A block cipher is an essential cryptographic algorithm to achieve confidentiality. This paper proposes parallel implementations of Korean block ciphers using Advanced Vector eXtension (AVX)-512, which is a new Single instruction, multiple data (SIMD) instruction set that has recently been integrated into several high-end Intel central processing unit (CPU). Target algorithms are LEA, HIGHT, and CHAM block ciphers. Additionally, this paper also proposes applicable implementing techniques, which are designed for each algorithm. These enable to use of parallel processing instructions in AVX-512 properly for each algorithm. The proposed LEA-128 (192, 256 resp.)implementation demonstrates a performance improvement of 506.09% (323.31%, 386.76% resp.) compared to the reference code, and our HIGHT implementation exhibits a performance improvement of 520.88% compared to the reference code. In addition, CHAM-64/128 (128/256 resp.) implementation shows a performance improvement of 1,325.81% (833.61% resp.) compared to the reference code. In addition, we measured the performance with a 32MB long message. LEA-128 (192, 256 resp.) implementation showed an improvement of 556.32% (594.74%, 615.38% resp.) compared with the reference code. Also, HIGHT implementation showed 834.40%, and CHAM showed 1,332.40% (832.86% resp.) for CHAM-64/128 (CHAM-128/256 resp.), compared by the reference code. To the best of our knowledge, this is the first result of the study to optimize Korean cryptographic algorithms using the AVX-512 instruction set. The proposed methods can effectively be used in Addition, Rotation, and XOR (ARX)-based cryptographic algorithms, enabling efficient cryptographic algorithm processing in various environments such as hash-based signatures, service environments, gateway, and edge computing.

Integration of a Real-Time CCSDS 410.0-B-32 Error-Correction Decoder on FPGA-Based RISC-V SoCs Using RISC-V Vector Extension

The Consultative Committee for Space Data Systems (CCSDS) recommends the use of short-block length Bose-Chaudhuri-Hocquenghem (BCH) and binary low-density parity-check (LDPC) codes. Despite the high error-correction capacity of non-binary low-density parity-check (NB-LDPC) codes, they have not yet been considered due to their high decoding complexity. In this paper, the feasibility of NB-LDPC coding for space telecommand link applications using a RISC-V soft-core processor plus a vector co-processor is demonstrated. The purpose of this work is to avoid the need for a dedicated decoder hardware, and thus the customized general-purpose processor which performs decoding can be reconfigured to perform other important on-board tasks. In this way, the logic utilization and power consumption can be reduced since more functionalities can be assumed by the on-board processor. The method of acceleration of a NB-LDPC decoder over GF(16) using the RISC-V vector extension is demonstrated, and a throughput of 8.48 kbps is achieved for the Forward-Backward implementation of the min-max decoding algorithm, which is compatible with the low-rate and mid-rate telecommand systems recommended by CCSDS.

Acceleration with long vector architectures: Implementation and evaluation of the FFT kernel on NEC SX‐Aurora and RISC‐V vector extension

SummaryNovel architectures leveraging long and variable vector lengths like the NEC SX‐Aurora or the vector extension of RISCV are appearing as promising solutions on the supercomputing market. These architectures often require re‐coding of scientific kernels. For example, traditional implementations of algorithms for computing the fast Fourier transform (FFT) cannot take full advantage of vector architectures. In this article, we present the implementation of FFT algorithms able to leverage these novel architectures. We evaluate these codes on NEC SX‐Aurora , comparing them with the optimized NEC libraries; and in a prototype of a RISC‐V core with a vector processing unit. We present the benefits and limitations of two approaches of RADIX‐2 FFT vector implementations. We show that our approach makes better use of the vector unit of the NEC SX‐Aurora , reaching higher or equal performance than the optimized NEC library. More generally, we prove the importance of maximizing the vector length usage of the algorithm, taking advantage of the FFT properties to reduce long‐latency vector operations, and reordering the instructions according to the specific hardware features to boost the performance of FFT‐like computational kernels.

Performance Left on the Table: An Evaluation of Compiler Autovectorization for RISC-V

Next-generation length-agnostic vector instruction set architecture (ISA) designs, the RISC-V vector extension, and ARM’s scalable vector extension enable software portability across hardware implementations with different vector engines. While traditional, fixed-length single-instruction–multiple-data ISA instructions, such as Intel AVX and ARM Neon, enjoy mature compiler support for automatic vectorization, compiler support is still emerging for these length-agnostic ISAs. This work studies the compiler shortcomings that constitute the gap in autovectorization capabilities between length-agnostic and fixed-length architectures. We examine LLVM’s support for both the RISC-V vector extension and traditional vector ISAs. We study a set of synthetic scalar loops to compare the breadth of support in the two settings, and we examine a real benchmark suite to compare autovectorized to hand-vectorized RISC-V code. We use both studies to distill a set of recommendations for engineering improvements and future research in compilers and programming models for length-agnostic vector programming.

Compiling for Vector Extensions With Stream-Based Specialization

To overcome the current performance wall, data streaming and data-flow computing paradigms have been gradually making their way into the general-purpose domain. However, the proliferation of such paradigms is often hindered by the lack of compilation support, as their execution model is usually incompatible with the internal static single-assignment form used in modern compilers. Accordingly, we propose a new compilation flow that leverages the LLVM infrastructure to automatically extract and encode the memory access pattern and computation data-flow graph with streaming representations. The proposed compilation flow is used to generate code for the recently presented Unlimited Vector Extension, which tackles the shortcomings of vector-length agnostic single-instruction multiple-data extensions by deploying a data streaming paradigm with implicit memory access and loop control. We show that our proposed tool is capable of detecting, representing, and vectorizing a much wider range of loop patterns than existing solutions while providing significant performance gains.

TianheGraph: Customizing Graph Search for Graph500 on Tianhe Supercomputer

As the era of exascale supercomputing is coming, it is vital for next-generation supercomputers to find appropriate applications with high social and economic benefit. In recent years, it has been widely accepted that extremely-large graph computation is a promising killer application for supercomputing. Although Tianhe series supercomputers are leading in the world-wide competition of supercomputing (ranked No. 1 in the Top500 list for six times), previously they had been inefficient in graph computation according to the Graph500 list. This is mainly because the previous graph processing system cannot leverage the advanced hardware features of Tianhe supercomputers. To address the problem, in this paper we present our integrated optimizations for improving the graph computation performance on our next-generation Tianhe supercomputing system, mainly including sorting with buffering for heavy vertices, vectorized searching with SVE (Scalable Vector Extension) on matrix2000+ CPUs, and group communication on the proprietary interconnection network. Performance evaluation on a subset of the Tianhe supercomputer (with 512 nodes and 196,608 cores) shows that our customized graph processing system effectively improves the graph search performance and achieves the BFS performance of 2131.98 GTEPS.

The p-adic Corlette–Simpson correspondence for abeloids

For an abeloid variety A over a complete algebraically closed field extension K of mathbb {Q}_p, we construct a p-adic Corlette–Simpson correspondence, namely an equivalence between finite-dimensional continuous K-linear representations of the Tate module and a certain subcategory of the Higgs bundles on A. To do so, our central object of study is the category of vector bundles for the v-topology on the diamond associated to A. We prove that any pro-finite-étale v-vector bundle can be built from pro-finite-étale v-line bundles and unipotent v-bundles. To describe the latter, we extend the theory of universal vector extensions to the v-topology and use this to generalise a result of Brion by relating unipotent v-bundles on abeloids to representations of vector groups.

Co-Design and System for the Supercomputer “Fugaku”

The supercomputer “Fugaku” is an exascale manycore-based parallel system developed as a Japanese national flagship supercomputer in the FLAGSHIP 2020 Project. While “Fugaku” was ranked first for several benchmarks such as TOP500, HPCG, HPL-AI, and Graph500 in 2020, the major design concept is the application-first concept by the co-design for power efficiency and high performance. We have designed an original manycore processor based on Armv8 instruction sets with the scalable vector extension, A64FX processor, with Fujitsu, our industry partner. The system consists of 158,976 nodes with 7.6 million cores in total and a theoretical peak of 537 Peta Floating-point Operations Per Second in double-precision floating points, connected by Tofu-D interconnect. The high performance computing (HPC)-oriented design enables an extremely good performance for memory-intensive workloads thanks to HBM2 memory with breakthrough power efficiency. In this article, we present the pragmatic practice of our co-design effort for “Fugaku” followed by an overview and the performance of “Fugaku.”

Highly Vectorized SIKE for AVX-512

It is generally accepted that a large-scale quantum computer would be capable to break any public-key cryptosystem used today, thereby posing a serious threat to the security of the Internet’s public-key infrastructure. The US National Institute of Standards and Technology (NIST) addresses this threat with an open process for the standardization of quantum-safe key establishment and signature schemes, which is now in the final phase of the evaluation of candidates. SIKE (an abbreviation of Supersingular Isogeny Key Encapsulation) is one of the alternate candidates under evaluation and distinguishes itself from other candidates due to relatively short key lengths and relatively high computing costs. In this paper, we analyze how the latest generation of Intel’s Advanced Vector Extensions (AVX), in particular AVX-512IFMA, can be used to minimize the latency (resp. maximize the hroughput) of the SIKE key encapsulation mechanism when executed on Ice Lake CPUs based on the Sunny Cove microarchitecture. We present various techniques to parallelize and speed up the base/extension field arithmetic, point arithmetic, and isogeny computations performed by SIKE. All these parallel processing techniques are combined in AvxSike, a highly optimized implementation of SIKE using Intel AVX-512IFMA instructions. Our experiments indicate that AvxSike instantiated with the SIKEp503 parameter set is approximately 1.5 times faster than the to-date best AVX-512IFMA-based SIKE software from the literature. When executed on an Intel Core i3-1005G1 CPU, AvxSike outperforms the x64 assembly implementation of SIKE contained in Microsoft’s SIDHv3.4 library by a factor of about 2.5 for key generation and decapsulation, while the encapsulation is even 3.2 times faster.

Using long vector extensions for MPI reductions

The modern CPU’s design, including the deep memory hierarchies and SIMD/vectorization capability have a more significant impact on algorithms’ efficiency than the modest frequency increase observed recently. The current introduction of wide vector instruction set extensions (AVX and SVE) motivated vectorization to become a critical software component to increase efficiency and close the gap to peak performance.In this paper, we investigate the impact of the vectorization of MPI reduction operations. We propose an implementation of predefined MPI reduction operations using vector intrinsics (AVX and SVE) to improve the time-to-solution of the predefined MPI reduction operations. The evaluation of the resulting software stack under different scenarios demonstrates that the approach is not only efficient but also generalizable to many vector architectures. Experiments conducted on varied architectures (Intel Xeon Gold, AMD Zen 2, and Arm A64FX), show that the proposed vector extension optimized reduction operations significantly reduce completion time for collective communication reductions. With these optimizations, we achieve higher memory bandwidth and an increased efficiency for local computations, which directly benefit the overall cost of collective reductions and applications based on them.

Polynomial multiplication on embedded vector architectures

High-degree, low-precision polynomial arithmetic is a fundamental computational primitive underlying structured lattice based cryptography. Its algorithmic properties and suitability for implementation on different compute platforms is an active area of research, and this article contributes to this line of work: Firstly, we present memory-efficiency and performance improvements for the Toom-Cook/Karatsuba polynomial multiplication strategy. Secondly, we provide implementations of those improvements on Arm® Cortex®-M4 CPU, as well as the newer Cortex-M55 processor, the first M-profile core implementing the M-profile Vector Extension (MVE), also known as Arm® Helium™ technology. We also implement the Number Theoretic Transform (NTT) on the Cortex-M55 processor. We show that despite being singleissue, in-order and offering only 8 vector registers compared to 32 on A-profile SIMD architectures like Arm® Neon™ technology and the Scalable Vector Extension (SVE), by careful register management and instruction scheduling, we can obtain a 3× to 5× performance improvement over already highly optimized implementations on Cortex-M4, while maintaining a low area and energy profile necessary for use in embedded market. Finally, as a real-world application we integrate our multiplication techniques to post-quantum key-encapsulation mechanism Saber