Variable-length Packets Research Articles

Fair and Efficient Packet Scheduling Using Resilient Quantum Round-Robin

Round-robin based packet scheduling algorithms are suitable for high-speed networks, but in a variable-length packet environment, this kind of scheduling algorithm need consider packet length to guarantee scheduling fairness. Previous schemes are not perfect for fairness and efficiency. This paper presents a new easily implementable scheduling discipline, called Resilient Quantum Round-Robin (RQRR), in which the quantum given to each of the flows in a round is not fixed and is calculated depending on the transmission situation of all the flows in the previous round. We prove that the implementation complexity of RQRR is O (1) with respect to the number of flows. We analytically prove the fairness properties of RQRR, and show that its relative fairness measure has an upper bound of 7Max-1, where Max is the size of the largest packets. Finally, we present simulation results comparing the fairness and performance characteristics of RQRR with deficit round-robin (DRR), which show that RQRR achieves better short time scale fairness and scheduling delay properties.

Fair and Efficient Variable-length Packet Scheduling and Multilink Transmission Support

Fair and Efficient Variable-length Packet Scheduling and Multilink Transmission Support

Improved performance analysis of Gigabit passive optical networks

Gigabit passive optical networks (GPON) provide a capacity boosts in both the total bandwidth and bandwidth efficiency through the use of larger variable-length packets in Passive Optical Networks technology. In this paper, we have described a purely-passive GPON compatible reach extender using distributed Raman amplification and reported the improved investigation through implementation of a square root module by a distance of 60km at data rate of 2.5Gbps. An efficient improvement in Q factor is achieved with square root module, which further helps in increasing the length of GPON.

Discrete Random Contention System with Variable Packet Length

The paper researches the random contention system in-depth using the average cycle method, then gets the formulas of the systemic throughput, free rate and collision rate with variable packet length. The simulation results verify the correctness of the theory, meanwhile, gets some conclusions that the different arrival rate G is how to affect the main source of the throughput with variable packet length. It has some researching significance. DOI: http://dx.doi.org/10.11591/telkomnika.v11i12.3697

Number of tunable wavelength converters and internal wavelengths needed for cost‐effective design of asynchronous optical packet switching system with shared or output fibre delay line buffer

Optical packet switching (OPS) is being considered as one of the switching technologies for a future optical internet. For contention resolution in an optical packet switching (OPS) system, the wavelength dimension is generally used in combination with a fibre delay line (FDL) buffer. In this study, the authors propose to reduce the number of tunable wavelength converters (TWCs) by sharing TWCs for cost-effective design of an asynchronous OPS system with a shared or an output FDL buffer. Asynchronous and variable-length packets are considered in the OPS system design. To investigate the number of TWCs needed for the OPS system, an algorithm is proposed, which searches for an available TWC and an unused internal wavelength, as well as an outgoing channel. This algorithm is applied to an OPS system with a shared or an output FDL buffer. Also, the number of internal wavelengths (i.e. the conversion range of the TWC) needed for an asynchronous OPS system is presented for cost reduction of the OPS system.

OpenFlow-Based Flow-Level Bandwidth Provisioning for CICQ Switches

Flow-level bandwidth provisioning (FBP) achieves fine-grained bandwidth assurance for individual flows. It is especially important for virtualization-based computing environments such as data centers. However, existing flow-level bandwidth provisioning solutions suffer from a number of drawbacks, including high implementation complexity, poor performance guarantees, and inefficiency to process variable length packets. In this paper, we study flow-level bandwidth provisioning for Combined Input Crosspoint Queued (CICQ) switches in the OpenFlow context. First, we propose the Flow-level Bandwidth Provisioning algorithm for CICQ switches, which reduces the switch scheduling problem to multiple instances of fair queuing problems, each utilizing a well-studied fair queuing algorithm. We theoretically prove that FBP can closely emulate the ideal Generalized Processing Sharing model, and accurately guarantee the provisioned bandwidth. Furthermore, we implement FBP in the OpenFlow software switch to obtain realistic performance data by a prototype. Leveraging the capability of OpenFlow to define and manipulate flows, we experimentally demonstrate a practical flow-level bandwidth provisioning solution. Finally, we conduct extensive simulations and experiments to evaluate the design. The simulation data verify the correctness of the analytical results, and show that FBP achieves tight performance guarantees. The experiment results demonstrate that our OpenFlow-based prototype can conveniently and accurately provision bandwidth at the flow level.

Heuristic performance model of optical buffers for variable length packets

Optical switching (optical packet switching, optical burst switching, and others) provides alternatives to the current switching in backbone networks. To switch optically, also packet buffering is to be done optically, by means of fiber delay lines (FDLs). Characteristic of the resulting optical buffer is the quantization of possible delays: Only delays equal to the length of one of the FDLs can be realized. An important design challenge is the optimization of the delay line lengths for minimal packet loss. To this end, we propose a heuristic based on two existing queueing models: one with quantization and one with impatience. Combined, these models yield an accurate performance modeling heuristic. A key advantage of this heuristic is that it translates the optical buffer problem into two well-known queueing problems, with accurate performance expressions available in the literature. This paper presents the heuristic in detail, together with several figures, comparing the heuristic's output to existing approaches, validating its high accuracy.

Novel FWM-Based Spectral Amplitude Code Label Recognition for Optical Packet-Switched Networks

We propose and demonstrate a novel architecture for four-wave mixing (FWM)-based recognition of spectral amplitude code (SAC) labels in optical packet-switched networks. With a proper code design, a unique FWM idler for each SAC label, referred to as a label identifier (LI), is generated in a nonlinear medium. A serial array of fiber Bragg gratings is then used to reflect the LI wavelengths. Each LI is associated with a unique amount of delay between two optical signals received at two photodiodes (PDs). Label recognition is then achieved by measuring this unique time delay (referred to as the characteristic delay). The main advantages of the proposed method include the following: no serial-to-parallel conversion is required, simple label extraction is achieved, variable-length packets are supported, and the number of PDs used in the label recognition module is reduced. Moreover, the LI wavelengths do not need to exhibit any periodicity or match a particular wavelength grid; this results in a less challenging code design with smaller spectral occupancy for label generation. An experiment is conducted, where two variable-length data packets are transmitted over a 50-km dispersion-compensated span and switched at a forwarding node. The SAC labels are successfully recognized, and we obtain error-free transmission for the switched packets with less than 0.3-dB penalty.

Performance Analysis of Packet Aggregation for IEEE 802.11 PCF MAC-Based Wireless Networks

In this paper, we investigate the effect of packet aggregation on the delay performance of the IEEE 802.11 Point Coordination Function (PCF) MAC. We intend to use packet aggregation to reduce polling overhead of 802.11 PCF and improve the delay performance. We consider two different polling schemes for assembling variable-length packets for transmission: poll once and multiple poll. An analytical model is developed for evaluating the queueing delay of packets at nodes using 802.11 PCF MAC for medium access. Based on this model, we derive several closed-form expressions for computing average delay and queue length. To verify the correctness of our analytical model, we also develop a simulator for the 802.11 PCF MAC. The simulation results well match the analytical results. Several quantitative examples are given for illustrating the reduced average delays under various load conditions and limits of aggregated frames. We find that the average delay decreases with the limit of aggregated frames. We also find that, between the two polling schemes, the multiple-poll scheme achieves a smaller average delay and queue length.

支持公平服务的CICQ 分层混合调度策略

Providing performance guarantees for arriving traffic flows has become an important measure for todays routing and switching systems. However, none of current scheduling algorithms built on CICQ (combined input and cross-point buffered) switches can provide flow level performance guarantees. Aiming at meeting this requirement, the feasibility of implementing flow level scheduling is discussed thoroughly. Then, based on the discussion, it comes up with a hybrid and stratified fair scheduling (HSFS) scheme, which is hierarchical and hybrid, for CICQ switches. With HSFS, each input port and output port can schedule variable length packets independently with a complexity of <italic>O</italic>(1). Theoretical analysis show that HSFS can provide delay bound, service rate and fair performance guarantees without speedup. Finally, we implement HSFS in SPES (switch performance evaluation system) to verify the analytical results.

Achieving fair service with a hybrid scheduling scheme for CICQ switches

Providing performance guarantees for arriving traffic flows has become an important measure for today’s routing and switching systems. However, none of current scheduling algorithms built on CICQ (combined input and cross-point buffered) switches can provide flow level performance guarantees. Aiming at meeting this requirement, the feasibility of implementing flow level scheduling is discussed thoroughly. Then, based on the discussion, it comes up with a hybrid and stratified fair scheduling (HSFS) scheme, which is hierarchical and hybrid, for CICQ switches. With HSFS, each input port and output port can schedule variable length packets independently with a complexity of O(1). Theoretical analysis show that HSFS can provide delay bound, service rate and fair performance guarantees without speedup. Finally, we implement HSFS in SPES (switch performance evaluation system) to verify the analytical results.

Huge capacity optical packet switching and buffering

We demonstrate 2.56 Tbit/s/port dual-polarization DWDM/DQPSK variable-length optical packet (20 Gbit/s × 64 wavelengths × 2 polarizations) switching and buffering by using a 2×2 optical packet switch (OPS) system. The optical data plane of the OPS system was constructed of multi-connected electro-optical switches and fiber delay lines. The accumulated polarization dependent loss of each optical path in the data plane was less than 5 dB. This low-polarization-dependence OPS system enabled us to handle DWDM/DQPSK optical packets (1.28 Tbit/s/port) with time-varying polarization after transmission through 100 km fiber in the field.

Node pacing for small optical RAM-buffered packet-switching networks

One of the difficulties with optical packet switched (OPS) networks is buffering optical packets in the network. The only available solution that can currently be used for buffering in the optical domain is using long fiber lines called fiber delay lines (FDLs), which have severe limitations. Moreover, the research on optical RAM presently being done is not expected to achieve a large capacity soon. However, the burstiness of Internet traffic causes high packet drop rates and low utilization in very small buffered OPS networks. We therefore propose a new node-based pacing algorithm for decreasing burstiness. We show that by applying some simple pacing at the edge or core backbone nodes, the performance of very small optical RAM buffered core OPS networks with variable-length packets can be notably increased.

A Scheduling Algorithm Based on Credit in Variable-length Packet Parallel Switching Network

A Scheduling Algorithm Based on Credit in Variable-length Packet Parallel Switching Network

Performance analysis of a metro WDM ring networks with variable-length packets under symmetric and asymmetric traffic

In this paper, we discuss and evaluate two proposed metro wavelength division multiplexing (WDM) ring network architectures for variable-length packet traffic in storage area networks (SANs) settings. The paper begins with a brief review of the relevant architectures and protocols in the literature. Subsequently, the network architectures along with their medium access control (MAC) protocols are described. Performance of the two network architectures is studied by means of computer simulation in terms of their queuing delay, node throughput and proportion of packets dropped. The network performance is evaluated under symmetric and asymmetric traffic scenarios with Poisson and self-similar traffic.

Contention resolution and variable length optical packet switching using the active vertical-coupler-based optical Crosspoint switch

We demonstrate packet detection at an optical switch input using an optoelectronic control system which then processes the headers of the packets, and controls the switching according to the header content for both fixed and variable length packets arriving synchronously or asynchronously at the optical switch. Furthermore, contention resolution is demonstrated in an optical Crosspoint switch by detecting packets at the input ports and controlling the switch operation accordingly. By incorporating this control system into the Crosspoint switch it is possible to route contending packets to a recirculating fibre delay line and to control the switch output in a flexible manner for any type of traffic depending on the applied switching algorithm. The feasibility of a recirculating buffer implementation is supported by the very low crosstalk characteristics of the Crosspoint switch. The experiments are done with 155 Mb/s headers and 10 Gb/s payloads transmitted on a single wavelength with a guard time of 12.8 ns between the header and the payload. Error-free photonic switching of fixed and variable length packets and contention resolution of fixed length packets are shown, with the main signal degradation being from the switch cell attenuation and amplified spontaneous emission (ASE) which can be alleviated by eliminating fibre-to-fibre transmission loss in the Crosspoint switch.

DSAR: A New Segmentation Scheme for Input Buffered Switches

Input Buffered switches can not directly deal with variable size packets. The variable length packets need to be segmented into fixed length cells before scheduling. Then segmentation and reassembly (SAR) must be used. The traditional SAR scheme can lead to significant loss of fabric bandwidth due to the padding bytes, which requires speed up in switch fabric to compensate for this bandwidth loss. The improved scheme called cell merging can reduce the bandwidth loss greatly but it has low scalability and it is difficult to select suitable merging size. In this paper, we propose a new method of SAR for Input buffered switches using the queue information of switches and can adjust the segment size dynamically. New scheme is suitable for different traffic model and can provide an excellent delay performance. We evaluate DSAR scheme using simulation, the results show that it outperforms existing segmentation schemes in Input Buffered switches.

Hybrid optoelectronic buffer using CMOS memory and optical interfaces for 10-Gbit/s asynchronous variable-length optical packets

A hybrid optoelectronic buffer consisting of a complementary metal-oxide-semiconductor (CMOS) memory and optical/optoelectronic interface devices is described. The interface devices: an all-optical serial-to-parallel converter (SPC), electrical-to-optical parallel-to-serial converter (PSC), and optical clock pulse-train generator (OCPTG) enable write-in/read-out of preamble-free asynchronous high-speed optical packets to/from CMOS memory, and consequently, flexible and highly functional processing of the packets with CMOS circuitry. A prototype hybrid optoelectronic buffer subsystem using a field programmable gate array (FPGA)-based memory and modules for the interface devices is developed and error-free write-in and read-out operation for 10-Gbit/s asynchronous variable-length optical packets is demonstrated.

A reflective semiconductor optical amplifier based all-optical header separator

An all-optical header extraction scheme based on the reflective semiconductor optical amplifier (RSOA) is presented, which can be used to process variable-length and bit-rate transparent packets. Through selecting the appropriate carrier-lifetime of the RSOA, the payload pulses obtain smaller gains than header pulses and are considered to be compressed. By using the reflective structure, the header pulses can acquire larger gains than the payload twice, and the contrast radio (CR) is improved. The simulation results show that the CRs can reach 22.8 dB and 18 dB for the packets with header pulses at the rates of 2.5 Gb/s and 10 Gb/s, respectively, and these values can be optimized through properly selecting the structure parameters, such as the small-signal gain and saturation energy.

Optical Router Control Architecture and Contention Resolution Algorithms Capable of Asynchronous, Variable-Length Packet Switching

This paper presents a new optical-label switching (OLS) router control plane controller for multihop asynchronous, variable-length packet switching incorporating fast, fair, and wavelength-aware arbitration. The proposed optical router controller implements efficient unicast/multicast packet contention resolution algorithms and channel scheduling schemes to resolve the data plane switch fabric contention. The paper evaluates the performance of proposed algorithms in a multihop OLS simulation network with self-similar traffic input under various traffic scenarios. The simulation results demonstrate that the proposed algorithms effectively improve the multihop OLS network performance. The hardware-efficient design and implementation of the proposed router controller and major modules are evaluated in terms of the area and delay for various switch sizes on a Xilinx XCV1000E field programmable gate array (FPGA) chip. Finally, this paper experimentally demonstrates the combined unicast and multicast video streaming enabled by the proposed OLS router control techniques over a label switching testbed with edge routers and realistic Ethernet/IP traffic input.