Variable Length Coding Research Articles

A Quick Tables Look-up Algorithm based on Hash Query for CAVLC Decoding

Aiming to solve the problem of long table look-up time in table look-up of CAVLC (Context-based Adaptive Variable Length Coding) for H.264/ AVC, a quick table look-up algorithm based on hash query (TLHQ) is proposed to reduce table look-up time for CAVLC decoding in this paper. The basic idea of the new algorithm is that it uses query technology of hash table to rapidly determine code length based on the number of zero in code prefix, As a result, it can save a lot of time of table looking-up and code judging. Experimental results show that our supposed new algorithm could reduce about 20% table look-up time and save 1056 byte storage space for CAVLC decoding in H.264/AVC.

The Video Encryption Scheme Based on Perceptual Encryption Algorithm in H.264 Standards

To meet the requirement of multimedia video transmission's safety and real-time, this paper provides a conclusion based on video encryption schemes of the encryption algorithm. The solution sorts video data into VLC(variable length code) and FLC(fix-length code) ,only choose to reconstruction images FLC compared to encrypt the important element of the operation. The analysis and the simulation results show that the encryption scheme is not only high safety but also low cost system.

A Tunable Encryption Scheme and Analysis of Fast Selective Encryption for CAVLC and CABAC in H.264/AVC

Recently, two fast selective encryption methods for context-adaptive variable length coding and context-adaptive binary arithmetic coding in H.264/AVC were proposed by Shahid In this paper, it was demonstrated that these two methods are not as efficient as only encrypting the sign bits of nonzero coefficients. Experimental results showed that without encrypting the sign bits of nonzero coefficients, these two methods can not provide a perceptual scrambling effect. If a much stronger scrambling effect is required, intra prediction modes, and the sign bits of motion vectors can be encrypted together with the sign bits of nonzero coefficients. For practical applications, the required encryption scheme should be customized according to a user's specified requirement on the perceptual scrambling effect and the computational cost. Thus, a tunable encryption scheme combining these three methods is proposed for H.264/AVC. To simplify its implementation and reduce the computational cost, a simple control mechanism is proposed to adjust the control factors. Experimental results show that this scheme can provide different scrambling levels by adjusting three control factors with no or very little impact on the compression performance. The proposed scheme can run in real-time and its computational cost is minimal. The security of the proposed scheme is also discussed. It is secure against the replacement attack when all three control factors are set to one.

Communication waveform properties of an exact folded-band chaotic oscillator

We interpret the waveform of an exact folded-band oscillator as an on–off keyed communication waveform. Unlike most nonlinear systems, this oscillator has a general analytic solution that allows for unusually exact analysis. Using this solution, we identify the key differences between a deterministic chaotic oscillation and an ideal on–off keying waveform to be (1) an inherent form of intersymbol interference and (2) a grammar restriction giving rise to a built-in variable length code. We define a simple coherent receiver based on a matched filter, and consider transmission in the presence of additive white Gaussian noise. Analytic expressions for upper and lower bounds on the probability of errors in receiving code letters are derived and shown to be consistent with numerical simulations.

Variable-length coding for performance improvement of asymptotically optimal unrestricted polar quantization of bivariate Gaussian source

This paper considers the application of variable-length coding using two unrestricted polar quantizers (UPQs) for performance improvement of unrestricted polar quantization for bivariate Gaussian source. We propose the use of two UPQs, both designed for the bivariate Gaussian source of unit variance, having different sizes of codebooks and different optimal compressor functions. We show that the fixed-rate UPQ is a subset of our model, and we perform rigorous optimization procedure in order to obtain optimal parameter values maximizing the signal to quantization noise ratio (SQNR) for the given average bit rate. In addition, we study how gain in SQNR over the fixed-rate UPQ depends on the average bit rate and we show that the gain ranges from 0.619dB to 0.869dB depending on the average bit rate. Discussion is also provided about the proposed quantizer complexity and its performance in comparison to Shannon limit. The proposed UPQ provides a sophisticated choice of average bit rate compared to the fixed-rate UPQ. Features of the proposed quantizer indicate that the obtained model should be of high theoretical and practical significance.

Practical speculative parallelization of variable-length decompression algorithms

Variable-length coding is widely used for efficient data compression. Typically, the compressor splits the original data into blocks and compresses each block with variable-length codes, hence producing variable-length compressed blocks. Although the compressor can easily exploit ample block-level parallelism, it is much more difficult to extract such coarse-grain parallelism from the decompressor because a block boundary cannot be located until decompression of the previous block is completed. This paper presents novel algorithms to efficiently predict block boundaries and a runtime system that enables efficient block-level parallel decompression, called SDM . The SDM execution model features speculative pipelining with three stages: Scanner, Decompressor, and Merger. The scanner stage employs a high-confidence prediction algorithm that finds compressed block boundaries without fully decompressing individual blocks. This information is communicated to the parallel decompressor stage in which multiple blocks are decompressed in parallel. The decompressed blocks are merged in order by the merger stage to produce the final output. The SDM runtime is specialized to execute this pipeline correctly and efficiently on resource-constrained embedded platforms. With SDM we effectively parallelize three production-grade variable-length decompression algorithms?zlib, bzip2, and H.264?with maximum speedups of 2.50× and 8.53× (and geometric mean speedups of 1.96× and 4.04×) on 4-core and 36-core embedded platforms, respectively.

FPGA based High Performance CAVLC Implementation for H. 264 Video Coding

Context-based adaptive variable-length coding (CAVLC) is an important feature of the latest video coding standard H.264/AVC. The coding technique using conventional CAVLC based on area efficient design, the second is on low power design architecture will lead to low throughput. In this paper, an efficient CAVLC design is proposed. The main concept is the FPGA based pipelining scheme for parallel processing of two 4x4 blocks. When one block is processed by the scanning engine to collect the required symbols, its previous block is handled by the coding engine to translate symbols into bit stream. Our block based pipelined architecture doubles the throughput of CAVLC at high bit rates. The proposed architecture can make a real time processing of 1920X1080 @ 30fps. With the synthesis constraint of a 200MHz clock using altera cyclone-II FPGA.

Hardware Accelerated Compression of LIDAR Data Using FPGA Devices

Airborne Light Detection and Ranging (LIDAR) has become a mainstream technology for terrain data acquisition and mapping. High sampling density of LIDAR enables the acquisition of high details of the terrain, but on the other hand, it results in a vast amount of gathered data, which requires huge storage space as well as substantial processing effort. The data are usually stored in the LAS format which has become the de facto standard for LIDAR data storage and exchange. In the paper, a hardware accelerated compression of LIDAR data is presented. The compression and decompression of LIDAR data is performed by a dedicated FPGA-based circuit and interfaced to the computer via a PCI-E general bus. The hardware compressor consists of three modules: LIDAR data predictor, variable length coder, and arithmetic coder. Hardware compression is considerably faster than software compression, while it also alleviates the processor load.

A Tables Look-up Algorithm based on Program Code for CAVLC Decoding

Aiming to solve the problem of high memory access and long table look-up time in table look-up of CAVLC (Context-based Adaptive Variable Length Coding ) for H.264/ AVC , a efficient look-up algorithm based on program code is presented in table look-up for CAVLC decoding in this paper, based on the analysis of the structure of CAVLC code table .The basic idea of this algorithm is that a method based on program code is designed to express fully all the VLCTs (unstructured Variable Length Coding Tables ) in CAVLC decoding. As a result, the decoded codeword in VLCTs can be gotten easily in a program execution way which can save a lot of memory access and table look-up time spent in CAVLC decoding. The simulation results show that the proposed scheme can not only save 100% memory access of table look-up in CAVLC decoding, but also reduce 45% table look-up time in CAVLC decoding without degrading video quality, only adding 2.7kb storage space.

High-throughput CAVLC architecture for real-time H.264 coding using reconfigurable devices

One of the encoding methods offered by H.264 AVC is context-based adaptive variable length coding (CAVLC). This paper presents a high-throughput hardware implementation of the CAVLC encoder. A dual-coefficient scanning phase is investigated and modified to improve the speed of the encoding phase. This improved scanning solution determines all the required data for the encoding phase to be completed in a minimized and constant number of clock cycles. In addition, an algorithmic approach for encoding levels is exploited to reduce hardware resource requirements. The modified scanning phase approach offers significant throughput capabilities for CAVLC: at 200 MHz, the architecture is capable of encoding 1,080 p video files at 95 fps.

An improved VLC-based lossless data hiding scheme for JPEG images

In this paper, a lossless data hiding scheme which directly embeds data into the bitstream of JPEG images is presented. For real cases, the JPEG code space is partly occupied, not all variable length codes (VLC) in the Huffman table are used during the JPEG image compression process. Thus, these unused VLCs can be made used of and data hiding can be performed by mapping one or more unused VLCs to one used VLC. Through analyzing the statistics of both used and unused VLCs, the proposed scheme can take full advantage of the unused VLCs by mapping Huffman codes according to a specific mapping strategy and reach higher capacity. The output stego image can keep exactly the same content as the original one and preserve the same file size, and if the file size is allowed to be enlarged, then our scheme can achieve a significant improvement of embedding capacity.

Low‐complexity multi‐standard variable length coding decoder using tree‐based partition and classification

MPEG-2 and H.264/AVC use variable length coding (VLC) to remove statistical redundancy. Representing the codeword table efficiently is thus an important issue to reduce hardware complexity, especially for multi-standard applications. In this study, the VLC tree is decomposed using sub-tree classification. The proposed algorithm reduces the amount of storage required for codewords. The proposed MPEG-2/H.264 VLC decoder has 11.9 K gates when synthesised to operate at 180 MHz. The gate count is 20% lower than the sum of gate count of individual H.264 and MPEG-2 VLC decoders.

Prefix Encoding by Means of the $(2,3)$-Representation of Numbers

A new family of universal self-synchronizable variable-length codes is introduced. This family is not a generalization or improvement of the existing prefix codes, but is based on a new method of integer representation in a mixed base using the radix-2 and the auxiliary radix-3. Upper length bounds for such codes are obtained. The asymptotic estimates for the (2,3)-encoding including the pointwise redundancy are also given. In particular, this implies that the average length of a (2,3)-codeword is shorter than that of Fibonacci code. Elias gamma and delta codes are adopted for the (2,3) -variant with asymptotically shorter codewords as against the original case. Improvement of gamma and delta encoding for all numbers is also presented. One of (2,3)-codes with high density is highlighted as a possible candidate for practical use in data compression. The (2,3) -codes are very simple to construct and they have evident features of strong robustness.

135-MHz 258-K Gates VLSI Design for All-Intra H.264/AVC Scalable Video Encoder

To satisfy the video application diversities, an extension of H.264/advanced video coding (AVC), called scalable video coding (SVC), is designed to provide multiple demanded video data via a single video encoder. However, constructed on the fundamental of H.264/AVC, the complexity of SVC is much higher than that of H.264/AVC. In this paper, a VLSI design for all-intra scalable video encoder is proposed to aim at efficient scalable video encoding. First, the memory bandwidth requirements for several encoding methods are analyzed to find out the best encoding method which can achieve best tradeoff between internal memory usage and external memory access. Afterward, an all-intra SVC encoder combined with several advanced techniques, including fast intra prediction algorithm, efficient syntax element encoding approach in context-adaptive variable-length coding, and hardware-efficient techniques, are implemented in a macroblock (MB)-level pipeline to increase data throughput. Implementation results demonstrate that our proposed SVC encoder can process more than 594-k MBs per second, which is equivalent to the summation of 60 high-definition, 1080-p, SD 480-p, and common intermediate format frames under 135-MHz working frequency. The proposed design consumes 258-K gate counts when synthesized by 90-nm CMOS technology.

Fast multiplerun_beforedecoding method for efficient implementation of an H.264/advanced video coding context-adaptive variable length coding decoder

We propose a fast new multiple run_before decoding method in context-adaptive variable length coding (CAVLC). The transform coefficients are coded using CAVLC, in which the run_before symbols are generated for a 4×4 block input. To speed up the CAVLC decoding, the run_before symbols need to be decoded in parallel. We implemented a new CAVLC table for simultaneous decoding of up to three run_befores. The simulation results show a Total Speed-up Factor of 205%∼144% over various resolutions and quantization steps.

An Efficient Overlapped LDPC Decoder with a Upper Dual-diagonal Structure

A low density parity check (LDPC) decoder provides a most powerful error control capability for mobile communication devices and storage systems, due to its performance being close to Shannon's limit. In this paper, we introduce an efficient overlapped LDPC decoding algorithm using a upper dual- diagonal parity check matrix structure. By means of this algorithm, the LDPC decoder can concurrently execute parts of the check node update and variable node update in the sum-product algorithm. In this way, we can reduce the number of clock cycles per iteration as well as reduce the total latency. The proposed decoding structure offers a very simple control and is very flexible in terms of the variable bit length and variable code rate. The experiment results show that the proposed decoder can complete the decoding of codewords within 70% of the number of clock cycles required for a conventional non- overlapped decoder. The proposed design also reduces the power consumption by 33% when compared to the non-overlapped design.

병행설계를 이용한 H.264/AVC의 DCT 및 CAVLC 하드웨어 구현

In this paper, DCT(Discrete Cosine Transform) and CAVLC(Context Adaptive Variable Length Coding) are co-designed as hardware IP with software operation of the other modules in H.264/AVC codec. In order to increase the operation speed, a new method using SHIFT table is proposed. As a result, enhancement of about 16(%) in the operation speed is obtained. Designed Hardware IPs are downloaded into Virtex-4 FX60 FPGA in the ML-410 development board and H.264/AVC encoding is performed with Microblaze CPU implemented in FPGA. Software modules are developed from JM13.2 to make C code. In order to verify the designed Hardware IPs, Modelsim program is used for functional simulation. As a result that all Hardware IPs and software modules are downloaded into the FPGA, improvement of processing speed about multiples of 16 in case of DCT hardware IP and multiples of 10 in case of CAVLC compared with software-only processing. Although this paper deals with co-design of H/W and S/W for H.264, it can be utilized for the other embedded system design.

An enhanced variable-length arithmetic coding and encryption scheme using chaotic maps

We enhance the simultaneous arithmetic coding and encryption scheme previously proposed by us. By encoding a block of variable number of symbols to a codeword within the length of the computation register, the operating efficiency has been substantially improved. Moreover, the compressed sequence is processed by an additional diffusion operation which strengthens the security of the original scheme by having higher key and plaintext sensitivities. Simulation results show that the enhanced scheme runs faster than the original scheme and the traditional compress-then-encrypt approach at a comparable compression performance.

Watermarking in H.264/AVC Compressed Domain Using CAVLC

A new real-time watermarking technique based on H.264/AVC video standard is proposed. The algorithm works in the compressed domain by embedding watermark bits into quantized DCT coefficients of 4×4 blocks of the I-frame during the Context-based Adaptive Variable Length Coding (CAVLC) process. CAVLC offers a lower computational complexity which is efficient to the algorithm. During watermark extraction, the entire video do not need to be decoded,which meets the requirement of the real-time processing.The scheme yields tiny bit-rate change after watermarking and the degradation of video quality is negligible. The simulation results show that watermark embedded is fragile and is easily distorted under attacks, which can be used for the video authentication or covert communication applications.

1-4 可変長符号化

1-4 可変長符号化