Variable Gain Research Articles

A Stroke-Limitation AMD Control System with Variable Gain and Limited Area for High-Rise Buildings

A Stroke-Limitation AMD Control System with Variable Gain and Limited Area for High-Rise Buildings

Variable Gain Impulsive Synchronization for Discrete-Time Delayed Neural Networks and Its Application in Digital Secure Communication.

This article revisits the problems of impulsive stabilization and impulsive synchronization of discrete-time delayed neural networks (DDNNs) in the presence of disturbance in the input channel. A new Lyapunov approach based on double Lyapunov functionals is introduced for analyzing exponential input-to-state stability (EISS) of discrete impulsive delayed systems. In the framework of double Lyapunov functionals, a pair of timer-dependent Lyapunov functionals are constructed for impulsive DDNNs. The pair of Lyapunov functionals can introduce more degrees of freedom that not only can be exploited to reduce the conservatism of the previous methods, but also make it possible to design variable gain impulsive controllers. New design criteria for impulsive stabilization and impulsive synchronization are derived in terms of linear matrix inequalities. Numerical results show that compared with the constant gain design technique, the proposed variable gain design technique can accept larger impulse intervals and equip the impulsive controllers with a stronger disturbance attenuation ability. Applications to digital signal encryption and image encryption are provided which validate the effectiveness of the theoretical results.

Synchronization issue of uncertain time-delay systems based on flexible impulsive control

<p>This paper discusses a synchronization issue of uncertain time-delay systems via flexible delayed impulsive control. A new Razumikhin-type inequality is presented, considering adjustable parameters the $ \varpi(t) $, which relies on flexible impulsive gain. For the uncertain time-delay systems where delay magnitude is not constrained to impulsive intervals, sufficient conditions for global exponential synchronization (GES) are established. Furthermore, based on Lyapunov theory, a new differential inequality and linear matrix inequality design, and a flexible impulsive control method is introduced through using the variable impulsive gain and time-varying delays. It is interesting to find that uncertain time-delay systems can maintain GES by adjusting the impulsive gain and impulsive delay. Finally, two simulations are given to illustrate the effectiveness of the derived results.</p>

Parameter-Estimation-Based Gain-Scheduling Control of Weight on Bit in Drilling Process With Uncertain Penetration Resistance Coefficient.

It is inevitable to encounter through different formations in the drilling process for deep exploration, and the penetration resistance coefficient (PRC) is an uncertain parameter related to lithology. In this article, a parameter-estimation-based gain-scheduling controller is developed to eliminate undesired system performance deterioration due to the uncertain parameter. First, a drill-string axial finite element model with the uncertain PRC is established, and a control-oriented low-order model is derived via mode selection. A gain-scheduling controller is computed based on the quadratic stability condition of the closed-loop system, which can cope with the system's parameter uncertainty using variable low-frequency gain. An adaptive observer is designed to estimate the unmeasurable scheduling variable. Field data from a geothermal drilling well is obtained to validate our model. According to this drilling well scenario, both numerical and experimental results illustrate the effectiveness of our method. The explicit relationship between the controller gain and the uncertain parameter is presented. It is found that the performance of the closed-loop system is more sensitive to the controller gain when drilling in soft formations, requiring more attention in such scenarios.

A 60 GHz Broadband LNA with Joined Variable Gain Control and Switching in 22 nm FD-SOI

A 60 GHz Broadband LNA with Joined Variable Gain Control and Switching in 22 nm FD-SOI

A Segmented Iterative Learning Scheme-Based Distributed Fault Estimation for Switched Interconnected Nonlinear Systems.

In this article, a distributed fault estimation (DFE) approach for switched interconnected nonlinear systems (SINSs) with time delays and external disturbances is proposed using a novel segmented iterative learning scheme (SILS). First, through the utilization of interrelated information among subsystems, a distributed iterative learning observer is developed to enhance the accuracy of fault estimation results, which can realize the fault estimation of all subsystems under time delays and external disturbances. Simultaneously, to facilitate rapid fault information tracking and significantly reduce sensitivity to interference, a new SILS-based fault estimation law is constructed by combining the idea of segmented design with the method of variable gain. Then, an assessment of the convergence of the established fault estimation methodology is conducted, and the configurations of observer gain matrices and iterative learning gain matrices are duly accomplished. Finally, simulation results are showcased to demonstrate the superiority and feasibility of the developed fault estimation approach.

Variable gain DNA nanostructure charge amplifiers for biosensing.

Electronic measurements of engineered nanostructures comprised solely of DNA (DNA origami) enable new signal conditioning modalities for use in biosensing. DNA origami, designed to take on arbitrary shapes and allow programmable motion triggered by conjugated biomolecules, have sufficient mass and charge to generate a large electrochemical signal. Here, we demonstrate the ability to electrostatically control the DNA origami conformation, and thereby the resulting signal amplification, when the structure binds a nucleic acid analyte. Critically, unlike previous studies that employ DNA origami to amplify an electrical signal, we show that the conformation changes under an applied field are reversible. This applied field also simultaneously accelerates structural transitions above the rate determined by thermal motion. We tuned this property of the structures to achieve a response that was ≈2 × 104 times greater (i.e., a gain or amplification) than the value from DNA hybridization under similar conditions. Because this signal amplification is independent of DNA origami-analyte interactions, our approach is agnostic of the end application. Furthermore, since large signal changes are only triggered in response to desirable interactions, we minimize the deleterious effects of non-specific binding. The above benefits of self-assembled DNA origami make them ideally suited for multiplexed biosensing when paired with highly parallel electronic readout.

78.8 pJ/b, 100 Mb/s Noncoherent IR-UWB Receiver for Multichannel Neurorecording Implants.

In this article, we present a novel approach for designing a low-power, low-area impulse radio ultra-wideband (IR-UWB) noncoherent receiver capable of achieving a data rate of 100 Mbps. Our proposed receiver demonstrates the ability to demodulate ON-OFF keying pulse streams across the entire lower frequency band defined by the Federal Communication Commission for UWB applications. The key components of the proposed receiver include a reconfigurable differential two-stage low-noise amplifier, a fully differential squarer, narrow-band interface rejection filters, and variable gain baseband amplifiers. These circuits work cohesively to ensure efficient signal reception and processing. To validate the performance of the proposed receiver, we implemented the design using TSMC 40-nm CMOS process technology. A short-range communication including a 1.5 cm tissue layer is tested utilizing a typical upconversion UWB transmitter fabricated in the same technology. Remarkably, the proposed receiver achieves a data rate of 100 Mbps with an impressively low energy efficiency of 78.8 pJ/b and occupies an area of 0.705 mm2. The compact size, remarkable energy efficiency, and high data rate capabilities of the proposed receiver meet the stringent requirements of neural recording implants.

Dynamic Range of a Digital Radio Receiver with a Photonic Analog-to-Digital Converter

The article is devoted to determining the requirements for the preliminary, analog part of the receiver and its structure when using a photonic ADC. The subject of research in this case is the issues of ensuring a large dynamic range of signals at the input of a receiver with a photonic ADC. The parameters and properties of the PADC with optical quantization and discretization are investigated. The distinctive features of the PADC are a high sampling rate, about 100 GHz, the possibility of increasing the carrier-to-noise ratio (CNR) and the effective number of bits (ENOB) due to the amplification of the carrier or modulating signal, and a low noise factor of microwave photonic elements. The presented advantages make it possible to reduce the structure of the analog part of the receiver by eliminating the mixer and anti-aliasing filter, as well as to achieve better sensitivity due to a lower level of internal noise. The study also revealed a limitation of the dynamic range imposed by the photonic element base. The reason for the limitation is the nonlinearity of the electro-optical modulators used and the limitation of the upper limit of the dynamic range to the photodetectors used. All this leads to requirements under which the analog part must provide significant amplification of the received radio signal, as well as the implementation of a variable gain. As a result, structural solutions are presented in the form of multichannel switching circuits. The principle of operation lies in the fact that each channel, consisting of a cascade of linear amplifiers and a PADC, has a different gain, and in the digital processing unit, channels are compared and switched depending on the signal level. At the same time, the level should be in the 'corridor' of acceptable values for the application of the PADC and within the dynamic range. The presented structural solutions will make it possible to implement radio receivers capable of receiving and processing a microwave signal without transferring the signal to an intermediate frequency. At the same time, the required signal amplification level of 105 - 106 can be achieved, which makes it possible to achieve a signal level of 2.5-9.5 V, at which the photonic analog-to-digital converter has the best CNR and ENOB indicators.

Neural tracking trajectory of discrete-time nonlinear systems based on an exponential sliding mode algorithm

For a class of discrete-time nonlinear systems, this paper proposes a discrete-time sliding mode control algorithm with an exponential term that acts as a variable gain to improve the convergence to a bounded region around the origin for the state variable. To compensate for unknown, but bounded disturbances, it has been employed a discontinuous function through a discrete-time integral action. A discrete-time neural network has also been employed to identify such nonlinear system with a block controllable structure. Finally, the proposed controller and the neural network algorithms are applied to a discretised direct current (DC) motor to follow a desired admissible trajectory. Numerical simulations show the effectiveness of the proposed control law.

SD-ARX modeling and robust MPC with variable feedback gain for nonlinear systems

As a generalized input-output model, the state-dependent exogenous variable autoregressive (SD-ARX) model has been intensively utilized to model complex nonlinear systems. Considering that more freedom can be provided by the state feedback control with variable feedback gain for constructing robust controllers, we propose a robust model predictive control (RMPC) algorithm with variable feedback gain on the basis of the SD-ARX model. First, the polytopic state space models (SSMs) of the system are constructed and the prediction accuracy of the SSMs is further improved by using the parameter variation rate information of the SD-ARX model. Then, an RMPC algorithm with variable feedback gain is synthesized for increasing the design freedom and enhancing the control performance. Two simulation examples, that is, the modeling and control of a continuous stirred tank reactor (CSTR) and a water tank system, are provided to demonstrate the feasibility and effectiveness of the proposed RMPC algorithm.

Dual-tuned high-swing variable-gain amplifier with enhanced dB-linear control

In this work, an analog-controlled variable gain amplifier (VGA) is proposed that demonstrates high linearity across a wide range of control voltages and low noise for analog front-end receivers. This work presents a dual-tuning technique utilizing diode-connected P-MOS load and pseudo-exponential approximation based source degeneration (DCPL-PESD), which enables simultaneous tuning of different control voltages to achieve the required dB-linear characteristic. The gain is increased by cross-coupling the input transistors of the differential pair. To extend the gain range, three single-stage VGAs are cascaded. The design and implementation of this VGA were carried out using the Cadence Virtuoso tool in 180 nm CMOS technology. Post-layout results indicate that the 3-stage cascaded VGA offers a gain range of 67.5 dB, of which 55 dB is dB-linear. By tuning the control voltage VC, it provides a continuous 18 dB dB-linear gain. The overall VGA consumes 0.232 mA from a 1.8 V power supply, with a power consumption of 417 μW. The bandwidth of 3-stage VGAs is measured as 46 MHz. The minimum input-referred noise (IRN) of this VGA is 4.158 nVHz. The total area, including the bias circuit and buffer, is 0.0054 mm2, and the output 1 dB compression point is −2.83 dBm at the gain of −1 dB.

Development of a low-cost, compact, wireless, 16 - channel biopotential data acquisition, signal conditioning and arbitrary waveform stimulator.

The health and fitness of the human body rely heavily on physiological parameters. These parameters can be measured using various tools such as ECG, EMG, EEG, EOG, among others, to obtain real-time physiological data. Analysing the bio-signals obtained from these measurements can provide valuable information that can be used to improve health-care in terms of observation, diagnosis, and treatment. In bio-signal pattern recognition applications, more channels provide multiple information simultaneously. Different biosignal acquisition devices are available in the market, most of which are designed for specific signals like ECG, EMG, EEG etc The gain of the amplifiers and frequency of the filters are designed as per the targeted signals; due to which one device cannot be used for other signals. Also, most of the systems are wired system which is not comfortable for animal studies. In this paper, a low-cost, compact, wireless, 16 channel biopotential data acquisition system with integrated electrical stimulator is designed and implemented. There are several novel and flexible design approaches were incorporated in the proposed design like (1) It has user selectable digital filter in each channel based on the signal frequencies like ECG, EMG, EEG, EOG. The same system will be used to acquire different signals simultaneously. (2) It has variable gain with a configurable analog bandpass filter. (3) It can acquire signals from 4 patients simultaneously. (4) The system is capable to acquire signal from both two-electrode as well as three-electrode configurations. (5) It has integrated stimulator with trapezoidal, charge-balanced, biphasic stimulus output with near zero DC level and user selectable pulse duration or frequency of the stimulus. The developed system has the ability to acquire and transmit data wirelessly in real-time at a high transfer rate. To validate the performance of the system, tests were conducted on the acquired signals using a simulator.

Layout Automation of Variable Gain Amplifier Circuit based on TCL Language

Layout Automation of Variable Gain Amplifier Circuit based on TCL Language

Pneumatic Bellows Actuated Parallel Platform Control with Adjustable Stiffness Using a Hybrid Feed-Forward and Variable Gain Integral Controller

Redundant cascade manipulators actuated by pneumatic bellows actuators are passively compliant, rugged and dexterous, making them exceptionally well suited for application in agriculture. Unfortunately, the bellows are notoriously difficult to precisely position. This paper presents a novel control algorithm for the control of a parallel platform actuated by pneumatic bellows, which serves as a module of a cascade manipulator. The algorithm combines a feed-forward controller and a variable-gain I-controller. The mathematical model of the module, which serves as the feed-forward controller, was created by applying two simple regression steps on experimentally acquired data. The gain of the I-controller is linearly dependent on the total reference error, thereby addressing the prevalent problem of “a slow response or excessive overshoot”, which, in the described case, the simple combination of a feed-forward and constant-gain I-controller tends to suffer from. The proposed algorithm was experimentally verified and its performance was compared with two controllers: an ANFIS controller and a constant gain PID controller. The proposed controller has outperformed the PID controller in the three calculated criteria: IAE, ISE and ITAE by more than 40%. The controller was also tested under dynamic loading conditions, showing promising results.

Implementation of a Robust PMAE Algorithm to Limit Large Gain Variation in a Fuel-Cell Integrated EV Charging Architecture

This paper proposes an adaptive error convergence technique to improve the charging dynamics of an electric vehicle (EV) charging system in a grid-integrated proton-exchange membrane fuel cell (PEMFC) architecture. The fuel cell is most often characterized by its slow dynamics during multiple load transients and preferably operated as an auxiliary energy source in EV charging architecture. The delayed response affects the overall charging dynamics with further controller phase lag and non-linear system parameters to induce a significant convergence error during reference command tracking. To effectively control multi-source integrated charging dynamics in an EV charging architecture, a projection-modified adaptive estimation (PMAE) algorithm is proposed in this paper. The control algorithm establishes a variable gain adaptation within a bounded error contour and updates the controller gains based on the tracking error dynamics gradient. The fuel cell, supporting other energy resources, provides a stronger charging resiliency with a duty-modified control technique at the EV charging station. To validate the effectiveness of the controller implementation, a grid-integrated multi-objective EV charging prototype is designed and developed for grid-to-vehicle (G2V) and vehicle-to-grid (V2G) at variable operating conditions.

Design and optimization of variable gain LNA for IoT applications using meta-heuristics search algorithms

In this paper, Variable Gain LNA (VG-LNA) parameters are optimized using the Particle Swarm Optimization (PSO), Firefly Algorithm (FA), and Genetic Algorithm (GA). A comparison of the three optimization techniques has been done and FA is depicting better results over GA and PSO. VG-LNA is composed of a Complementary Common Gate (CCG) and Variable Gain Amplifier (VGA). Gm-boost topology helps in increasing the gain while the current reuse technique provides less power consumption. Optimization algorithms simulated on MATLAB and the result shows minimum Noise Fig. (NF) is 2.62 dB, maximum gain is 17.8 dB, S11 i.e. input reflection coefficient is −13.5 dB and S22 i.e. output reflection coefficient is −14.7 dB at 50 Ω impedance matching while Figure of Merit1 (FoM1) is 36.14 dB using FA. The FA optimized parameters when simulated on Cadence Virtuoso software using GPDK 45 nm CMOS technology for the frequency range of 26–32 GHz then results show a minimum NF of 2.6 dB at 30.9 GHz, maximum gain of 16.9 dB at 30.5 GHz, S11 is −17.7 dB at 30.5 GHz, S22 is −21.2 dB at 29 GHz and FoM1 of 34.19 dB. The layout of the realized circuit has an area of 231.695 μm*164.48 μm i.e. 0.03811mm2.

An integrated LNA‐phase shifter in 65 nm CMOS for Ka‐band phased‐array receivers

SummaryIn this paper, a vector‐sum phase shifter (VSPS) integrated with a wideband high‐gain low‐noise amplifier (LNA) for Ka‐band phased‐array receivers is presented. The digitally controlled VSPS based on the RF phase shifting architecture consists of a modified I/Q signal generator with additional inductor resonance and a programmable variable gain amplifier (VGA) based on Four 3 × 4 transistor arrays. Besides the reduced parasitic effect of the I/Q signal generator, an Equidistant Contraction Technology (ECT) is used in the VGA, to maintain higher phase shift accuracy of the VSPS. A multistage LNA with series inductor peaking is adopted to fulfill the flat wideband gain, where LC resonance networks are used as interstage matching to compensate for gain roll‐off at a higher frequency. Based on simulations in 65 nm CMOS technology, the presented LNA‐Phase shifter has achieved an average NF of 3.24–3.66 dB, and an average gain of 13.1–23.6 dB. Moreover, an RMS phase error of 1.1–12.6°, an RMS gain error of 4.2–5.6 dB, and an RMS magnitude error of 2.1–2.8 dB are maintained across 27–40 GHz, with a 360° phase shift coverage in steps of approximately 2.8125°. The chip consumes 16.83 mW from a 1.2 V supply voltage, and the occupied area is 0.65 mm2.

Design of a 39-GHz compact bi-directional variable gain amplifier in 65-nm CMOS

This paper presents a differential two-stage 39-GHz bi-directional variable gain amplifier (Bi-VGA) for 5G mm-Wave applications. Based on a phase compensated bi-directional structure with tail current tuning technique, a variable gain cell with small phase variation and compact area is realized. To boost the gain and ease the impedance matching, the cross-coupled transistor pairs are adopted. Analysis and simulations are undertaken to illustrate the working mechanism of accurate gain control and low phase variation. The measured Bi-VGA achieves peak gain of 15.6 dB with 3-dB bandwidth over 35–45 GHz, covering the 5G 39-GHz band (37–43.5 GHz), and a maximum OP1dB of 3.5 dBm. Fabricated in 65-nm CMOS process, the Bi-VGA consumes 67 mW from a 1.2 V power supply with a small core area of 0.46 × 0.14 mm2, and its minimum noise figure is about 6.4 dB at the maximum gain state. Across a gain tuning range of 12 dB, the phase variation is less than 6.1° over the operating frequency range.

A fast-locking low-reference spur cascaded PLL with gate-diffusion input-based phase detector and pulse width amplifier

ABSTRACT This paper presents a newly proposed high-order cascaded phase-locked loop using a type-I phase-locked loop in the second stage. The type-I phase-locked loop includes a gate-diffusion-input-based phase detector and pulse width amplifier that leads to breaking the trade-off between reference spur and locking time. Moreover, a type-I phase-locked loop deploys a pulse width amplifier after a gate-diffusion-input-based phase detector with variable gain to amplify the phase error between the reference clock and the output of the voltage-controlled oscillator. The proposed architecture has been implemented in a 180-nm semiconductor laboratory CMOS technology. The proposed fifth-order cascaded phase-locked loop achieves the reference spur of −77 dBc, while the conventional first-stage charge-pump-based phase-locked loop achieves −59.7 dBc. It measures the 1.2 s settling time, whereas conventional first stage charge-pump-based phase-locked loop measures 2.4 s settling time. The cascaded phase-locked loop operates at 2.4 GHz output frequency, and the simulated phase noise at 1 MHz offset frequency is −105.4 dBc/Hz. It consumes 5.8 mW from a 1.8 V power supply.