Variable Digital Filters Research Articles

RCVM‐ASS‐CICSKA‐PAPT‐VDF: VLSI design of high‐speed reconfigurable compressed Vedic PAPT‐VDF filter for ECG medical application

AbstractDuring signal acquisition, the signals are impacted by multiple noise sources that must be filtered before any analysis. However, many different filter implementations in VLSI are dispersed among many studies. This study aims to give readers a systematic approach to designing a Pipelined All‐Pass Transformation based Variable digital filter (PAPT‐VDF) to eliminate the high‐frequency noise from ECG data. The modified design emphasizes first‐ and second‐order responses to obtain high‐speed filter realization with high operating frequencies. The addition of adder and multiplier designs to the hardware architecture of a filter design improves performance. The fundamental blocks of the filter design are the adder and multiplier. The adder and multiplier are employed with an Adaptable stage size‐based concatenation, incremented carry‐skip adder (ASS‐CICSKA), and Improved reconfigurable compressed Vedic multiplier (IRCVM). Utilizing the adder design diminishes the delay with enhanced performance because receiving the carry from an incrementation block is not mandatory. In the multiplier design, the compressor and the reconfigurable approach are adapted with a data detector block to detect the redundant input and lower the logic gates' switching activity with less area overhead. The proposed filter design is implemented in vertex 7 FPGA family device, and the performance measures are analyzed regarding area utilization, delay, power, and frequency. Also, by using the denoised signal, the mean square error (MSE), and signal‐to‐noise ratio (SNR) are evaluated in the MATLAB platform.

Energy efficient enhanced all pass transformation fostered variable digital filter design based on approximate adder and approximate multiplier for eradicating sensor nodes noise

Energy efficient enhanced all pass transformation fostered variable digital filter design based on approximate adder and approximate multiplier for eradicating sensor nodes noise

Generalised strategy for stabilising minimax-type variable bandpass filter

ABSTRACT This paper first develops a novel transformation-based strategy for guaranteeing the stability of recursive-type variable digital filters, and then presents a new type of functions called less-than-unity (LTU) functions required in performing stability-guaranteed parameter transformations (LTU transformations). The LTU transformations can be viewed as the generalised existing one. Based on the LTU transformations, a recursive bandpass filter with variable passband-width (PBW) is attained using the minimax criterion so that the stability is ensured. The recursive bandpass filter has continuously PBW and fixed passband centre frequency. To meet the stability condition of the recursive variable PBW bandpass filter (variable-PBW filter), the LTU parameter transformations are incorporated into the minimisation of the maximum amplitude-response error. It can be proved that incorporating the LTU transformations into the design process definitely produces a recursive variable-PBW filter whose stability is absolutely guaranteed. For verifying the ensured stability and demonstrating the high design accuracy, detailed computer simulations are included. The illustrative example verifies that the obtained variable-PBW filter not only has definitely ensured stability, but also its approximation accuracy is extremely high.

FPGA design of arithmetic optimised APT-VDF using reusable Vedic multiplier with simplified combinational logics for medical signal denoising

ABSTRACT All-pass transformation (APT)-based variable digital filters (VDFs) can be used in different biomedical signal-processing applications, particularly in electrocardiograph denoising. In this paper, arithmetic optimised APT-VDF is proposed by modifying the hardware structure of APT-VDF based on arithmetic perception to enhance the performance in terms of area, speed and power consumption. The core blocks of the suggested Arithmetic Optimised APT-VDF (AOAPT-VDF)are adders and multipliers. This paper introduces a new reusable Vedic multiplier with redundant detection unit to identify redundant computations while generating the partial products. Also, a new Carry select adder (CSLA) with simplified combinational logics is proposed to improve the performance of the CSLA by simplifying the partial sum and carry generation logics without requiring Ripple Carry Adders. The proposed Reusable Vedic Multiplier with Redundant Detection Logic (RVM-RDL) also reuses the same vertical and cross-product generation units repetitively to reduce the area while increasing the bit length. The effectiveness of the suggested AOAPT is analysed utilising the MIT-BIH Arrhythmia Database. The proposed AOAPT-VDF consumes only 0.21 W power and achieves a 235.50 MHz operating frequency.

Improved State-Space All-Digital Filters via Series Approximations

Recently, variable digital filters (VDFs) have become an essential research topic. This paper presents a simple method for the design of infinite impulse response (IIR) VDFs with high tuning accuracy. First, VDFs were created using a state-space model based on a frequency transformation, which requires the inverse matrix and the square root that leads to high computational cost. Then a new algorithm was implemented to generate the same VDFs absent the complex calculations that utilized negative binomial and Taylor series approximations in a simple state-space formulation. This algorithm provides high-accuracy approximations of the inverse matrix and square root compared to other algorithms that have been developed. Thus, the proposed VDFs have high tuning accuracy with respect to finite wordlength effects.

On the Design of Variable Filtered-OFDM Based LDACS for Future Generation Air-to-Ground Communication System

L-band digital aeronautical communication system (LDACS) has been newly presented for air-to-ground communication (A2GC) environment which is essentially based on orthogonal frequency division multiplexing (OFDM) scheme. This brief presents an innovative variable filtered-OFDM (VF-OFDM) based LDACS with the aid of variable digital filter utilizing the theory of Farrow structure and innovative interpolated band-pass method. Experimental observation has demonstrated that the resultant response of the filter satisfies the standard specification of LDACS spectral mask for different interpolation factors. It has also been shown that proposed VF-OFDM based LDACS system exhibits superior performance in terms of bit error rate (BER) and power spectral density (PSD) when compared to OFDM and F-OFDM based LDACS. Finally, superiority of the suggested architecture has been established by implementing it on Cyclone IV FPGA board.

VLSI design of APT-VDF using novel variable block sized ternary adder and multiplier

Nowadays, Variable digital filters (VDF) play an essential role in the field of communication and signal processing. The desired frequency response of any prototype filter can be obtained by developing an All Pass Transformation (APT) based Variable digital filter (APT-VDF) that maintains an exhaustive control over the cut off frequency. The performance of the APT-VDF is limited by its speed and area utilization. In this paper, the pipelined APT-VDF is modified by developing a new Variable Block Sized Ternary Adder (VBS-TA) and a modified Ternary multiplier for the fast realization of the filter structure. Because, the fundamental arithmetic operations involved in the design of APT-VDF are addition and multiplication. The ternary logic transmits more data through interconnection wire, and hence the ternary logic based arithmetic requires fewer components and interconnections. The proposed VBS-TA increases the speed of the addition process by skipping the carry propagation with the help of ternary compound gates. This VBS-TA can also be used to boost up the speed of the multiplier circuit in the APT-VDF filter. Furthermore, the ternary multiplier is modified by introducing a divide and conquers approach in the partial product generation part. The simulation results show that the proposed APT-VDF overtakes the existing VDFs in terms of delay, power and area utilization. It consumes only 0.289Wpower with a latency of 9.24 ns. Also, it achieves an operating frequency of 210.87 MHz, and it is much better than the existing VDFs.

Wayside acoustic detection of train bearings based on an enhanced spline-kernelled chirplet transform

Wayside acoustic detection is an effective and economical technology for fault diagnosis of train bearings. However, the technology has two main problems: Doppler Effect distortion, and high-level noise interference particularly harmonic interference. To solve both problems, a novel wayside acoustic detection scheme using an enhanced spline-kernelled chirplet transform (ESCT) method is proposed in this paper. Combining the spline-kernelled chirplet transform, built-in criterions, and a variable digital filter, the ESCT method is proposed for use in the extraction of the main harmonic components and corresponding instantaneous frequencies (IFs). This way, the residual signal, free of harmonic interference, can be obtained by excluding harmonic components in the raw acoustic signal using the ESCT method. The excluded harmonic components can be used to obtain motion parameters of the test train using a new estimation method. A resampling time vector can be constructed based on the estimated motion parameters. Doppler Effect in the residual signal can be reduced by using the time-domain interpolation resampling (TIR) method. Finally, spectral kurtosis (SK) is applied to extract train bearing fault features from the Doppler-free signal. By observing the Hilbert envelope spectrum of the filtered signal, train bearing faults can be detected. Comparing this approach with other schemes, the proposed solution requires comparatively little prior information and is easily applied to existing detection systems. The simulation and field experiments were conducted in this paper and results verified the effectiveness of the proposed method.

A novel Doppler Effect reduction method for wayside acoustic train bearing fault detection systems

Wayside acoustic detection of train bearing faults plays a significant role in maintaining safety in the railway transport system. Due to the relative movement between the train and the detection system, the collected acoustic signals are distorted by the Doppler Effect which results in frequency-domain distortion. Combining the multi-scale chirplet path pursuit (MSCPP) method, a variable digital filter (VDF), and a new motion parameter estimation method, a novel Doppler Effect reduction method is proposed. This can be used by wayside acoustic monitoring systems to improve detection system for train bearing faults, as illustrated in this paper. The MSCPP method with the build-in criterions is firstly used to estimate the instantaneous frequencies (IFs) of harmonic components in the wayside acoustic signals. Next, VDFs whose centre frequencies are the fitted IFs are constructed to exclude harmonic components. Using these, residual signals, free of strong harmonic interferences, can be obtained. At the same time, the motion parameters can be obtained by using a recently developed estimation method based on fitted IFs. The residual signal is then resampled to reduce the Doppler Effect by using the resampling time vector constructed using those estimated motion parameters. Finally, any bearing fault features can be extracted using the spectral kurtosis (SK) method. The effectiveness of the proposed signal processing method is verified by simulation and field-based experiments, as demonstrated in this paper.

WLS optimal design for variable FIR filters with continuous parameter of fractional delay

A spectral parameterization method with discretization parameters will meet a tradeoff between the design accuracy and computational effort when designing a variable digital filter. Thus, a continuous spectral parameterization method is presented for obtaining the WLS optimal coefficients of variable fractional delay filters. Separated non-negative weighting function and some characters of matrix and matrix operations are applied to derive a closed-form solution, and Cholesky factorization is adopted to avoid the numerical problem of computing the inverses of a matrix. Its high accuracy and considerably reduced computational complexity of the proposed algorithm are experimentally verified. The given FIR filters can found their applications in high accuracy dynamic time compensation.

Low Latency Area-Efficient Distributed Arithmetic Based Multi-Rate Filter Architecture for SDR Receivers

In software defined radio (SDR) receivers, sample rate conversion (SRC) and channelization are two computational intensive tasks. Coefficient-less cascaded-integrator-comb (CIC) filters achieve SRC with low computational complexity, but the design of its gain droop compensation filter involves coefficients. These coefficients vary with the change in radio standards. In this paper, an architecture for variable digital filter (VDF) for gain droop compensation employing a set of fixed coefficient sub-filters and multi-dimensional polynomials in terms of spectral parameters is realized based on distributed arithmetic (DA). As the coefficients in the sub-filters are fixed, the proposed method uses ROM-based LUTs giving rise to low computational complexity. The proposed DA–VDF filter is synthesized on an application specific integrated circuit (ASIC) employing CMOS 90[Formula: see text]nm technology using Synopsis Design Complier. The proposed architecture achieves low latency at a reduced area delay product (ADP) of 78% and an efficiency of 72% in energy per sample (EPS) when compared with the conventional MAC-based architecture.

Design and Implementation of Low Complexity 2-D Variable Digital FIR Filters Using Single-Parameter-Tunable 2-D Farrow Structure

In this paper, a novel single-parameter-tunable 2-D Farrow structure is proposed and used for implementing linear phase 2-D variable digital filters (VDFs) with tunable spectral characteristics. Real-time tunability in the spectral characteristics of the 2-D filter is achieved by varying a single tunable parameter in a fixed hardware structure. The proposed structure enables the realization of multiple 2-D filters from a single structure with minimum error and hardware complexity. The reduction in the hardware complexity becomes pronounced when the number of 2-D filters included in the 2-D VDF increases. The proposed structure is capable of efficiently realizing circularly symmetric and fan-type variable 2-D filters, which is demonstrated using different design examples. Results show that the proposed approach ensures up to 60% reduction in the hardware complexity when compared with the state-of-the-art approaches used for the design and implementation of 2-D VDFs. The proposed approach ensures a drastic reduction in the hardware complexity without sacrificing the accuracy with a normalized root mean square error less than 0.5%.

English

English

A novel design and implementation technique for low complexity variable digital filters using multi-objective artificial bee colony optimization and a minimal spanning tree approach

Farrow structure in canonic signed digit (CSD) space is an efficient approach for the design of real-time tunable finite precision variable digital filters (VDFs). A novel design method for Farrow structure based VDFs in CSD space with reduced hardware complexity is proposed in this paper. The design approach makes use of the multi-objective artificial bee colony (MOABC) optimization algorithm with an integer search space to find the optimal Farrow sub-filter coefficients. Further, a novel low complexity implementation approach for the finite precision VDF using a minimal spanning tree approach is also proposed. The minimal spanning tree approach deploys the shift inclusive differential coefficients (SIDCs) and the different shifted SIDCs with common sub-expression elimination (CSE) to optimize the multiple constant multiplications involved in the filter realization. The attractive feature of our proposed method using MOABC and SIDCs with CSE lies in the increased hardware complexity reduction of the VDFs, compared to the existing methods, which in turn reduces the hardware resource utilization and power consumption drastically compared to the continuous coefficient VDFs. The hardware implementation of the VDF using the proposed method has also been done using Xilinx ISE to analyse the reduction in the hardware complexity and dynamic power.

Stability-Guaranteed Two-Phase Design of Odd-Order Variable-Magnitude Digital Filters

Guaranteeing the stability is one of the most critical issues in designing a variable recursive digital filter. In this paper, we first present an odd-order recursive variable model (transfer function) that is used for designing an odd-order variable-magnitude (VM) digital filter, and then we replace the original coefficients of the denominator of the odd-order transfer function with a set of new parameters. These new parameters can ensure that they can take arbitrary values without incurring instability of the designed odd-order VM filter. To make the VM filter coefficients variable, we find all the VM filter coefficients as polynomial functions of the tuning parameter, which includes two phases. The first phase designs a set of recursive digital filters with fixed coefficients (constant filters), and the second phase utilizes a curve-fitting scheme to represent each coefficient as a polynomial function. As a result, the VM filter coefficients become variable, and the proposed parameter-substitution-based denominator coefficients ensure the filter stability. This is the most important contribution of the parameter-substitution-based design scheme. This paper uses the fifth-order demonstrative example to verify the stability guarantee as well as the design accuracy of the obtained the fifth-order VM filter.

Variable state-space digital filters using series approximations

This paper proposes new state-space formulations of IIR Variable Digital Filters (VDFs) based on frequency transformations. The existing frequency transformation-based state-space VDFs require restrictions on the transfer functions, state-space representations, and tuning characteristics. On the other hand, the proposed method is free from such restrictions. We achieve this goal by applying series approximations to the conventional state-space formulations of frequency transformations. This approach also allows us to realize the proposed VDFs without complicated computations such as the inverse matrix and the square root. Furthermore, the proposed VDFs show high accuracy with respect to the finite wordlength effects as well as the approximation errors.

SVD based reconfigurable SRC filter for multi‐standard radio receivers

With the recent growth in wireless industry, and changes that occur at a faster pace in radio standards, software defined radio (SDR) provides a flexible solution when compared with hardware radios. Channelisation and sample rate conversion (SRC) are two computational intensive tasks to be carried out in SDR receivers. Reconfigurable anti-aliasing filter and channeliser with minimum reconfiguration overhead is needed for the design of SDR receivers. Low complexity, coefficientless cascaded-integrator-comb filters provides flexible reconfiguration for SRC over a wide integer range, but offers gain droop in the passband of interest. Moreover, they are not suitable for achieving SRC by fractional rates. In this study, the authors propose the design of variable digital filter (VDF) for gain droop compensation and fractional SRC to meet the spectral characteristics of multiple radio communication standards, employing singular value decomposition algorithm. The proposed design of VDF is tested for its reconfigurability with four radio standards, namely, GSM900, WCDMA/CDMA 2000 and WiMAX 802.16. Simulations carried out in MATLAB showed that the proposed VDF had improved spectral response in comparison to other methods proposed in literature.

Variable delay digital comb filter extraction of weak phase signals for SSVEP

Abstract This study presents denoising of phases signal by comb filter. Signal phase is widely used in biomedical and communications engineering, and has become increasingly important over the past few years. In particular, steady-state visual evoked potential (SSVEP) of electroencephalogram (EEG) and quadrature amplitude modulation (QAM) uses phase to distinguish channel and data. For signal processing, the filter is usually adopted. In this study, the usefulness of comb and bandpass filters in detecting the phase of a signal is compared by using simulated and real signals to verify phase signal denoising. Experimental data show that comb filters had a higher signal to noise ratio (SNR) of phase signal. However, even if a comb filter performs well, the delay time of a digital comb filter will be limited by the sampling rate. It is possible to solve this problem, but doing so is inconvenient within the context of real-time applications. Using a variable delay (VD) approached to fractional delay for digital comb filter, it is both simple and easy to use.

Design and Implementation of High-Speed All-Pass Transformation-Based Variable Digital Filters by Breaking the Dependence of Operating Frequency on Filter Order

All-pass transformation (APT)-based variable digital filters (VDFs), also known as frequency warped VDFs, are typically used in various audio signal-processing applications. In an APT-based VDF, all-pass filter structures of appropriate order are used to replace the delay elements in a prototype filter structure. The resultant filter can provide variable frequency responses with unabridged control over cutoff frequencies on the fly, without updating the filter coefficients. In this brief, we briefly review the first- and second-order APT-based VDFs along with their hardware implementation architectures, and provide generalized design procedures to realize them as per required specifications. We also propose the modified pipelined hardware implementation architectures for both the first- and second-order APT-based VDFs. Field-programmable gate array implementation results of different first- and second-order APT-based VDF designs for both nonpipelined and pipelined implementation architectures are presented. An analysis of the results shows that the proposed pipelined implementation architectures result in high-speed VDFs, achieving high operating frequencies that are independent of the prototype filter order, for both the first- and second-order APT-based VDF designs.

Design of recursive variable digital filters with theoretically guaranteed stability

ABSTRACTStability is one of the most concerned issues in designing a recursive variable digital filter (VDF). This is because the coefficients of a recursive VDF constantly vary in the tuning process, and updating the coefficients may incur instability. Thus, an appropriate measure needs to be taken for ensuring its stability. This paper presents a new coefficient transformation (CT) method for transforming the coefficients of a recursive transfer-function denominator into a set of new coefficients. From the viewpoint of conventional constant-coefficient filter (constant filter) design, the new coefficients can take arbitrary values without incurring instability. For designing a stable VDF, we apply this CT to the variable case and approximate each transformed coefficient as a distinct polynomial in the tuning parameter. Thus, we can change the filter coefficients by changing the value of the tuning parameter, and thus tune the magnitude response. Thanks to the proposed CT, updating the filter coefficients will never incur instability. This is the core part of the CT-based design approach. In this paper, we utilise a weighting function to ignore the transition-band errors and thus enhance the design accuracy of important frequency bands (passband and stopband). Moreover, the polynomials use different degrees so as to reduce the VDF complexity. Two design examples (lowpass VDF and bandpass VDF) are provided for verifying the design accuracy and checking the stability.