Vapour Phase Reflow Soldering Research Articles

Improving efficiency of vapour phase soldering ovens with pressure and temperature-based process monitoring

During vapour phase reflow soldering used in electronics manufacturing, the process control of ovens is usually based on temperature measurements, which can be insufficient due to the saturation differences in the temperature and the vapour concentration. Therefore, the ovens use extended cycle times for process identification to ensure the proper formation of solder joints. This study offers a solution to eliminate the idle time by investigating the hydrostatic pressure conditions in the process zone. A pressure measurement system was developed for vapour phase soldering ovens which can monitor the vapour pressure changes by a gauge-type pressure sensor with fused temperature measurement. It works as an IoT-enabled node for data logging and subsequent control. The fusion of the hydrostatic pressure values with the temperature values allowed us to identify and reduce the idle time by approximately 60 s, which is 15–20% of the total soldering cycle time. This increases the oven's yield by 15–20%, reduces the system's power consumption by 15–20%, and reduces time above liquidus of the solder by ∼35%. The presented method could enhance the more sustainable electronics production according to the Sustainability Development and could improve the quality and reliability of the lead-free solder joints.

Compact numerical modelling of transient condensate layer formation on small components during vapour phase soldering

In this paper transient condensation and heat transfer been investigated on a printed circuit board (PCB) and a surface mounted (SMD) capacitor during a vapour phase reflow soldering (VPS) process. Classic VPS processes provide rapid heating with high heat transfer coefficient rates due to condensation that forms a continuous liquid film on the surfaces. Our aim was to develop a simple and fast computable method that, instead of relying on static descriptions, can reproduce the transient dynamics of the process. It was defined as an inverse heat conduction problem (IHCP) and proposed a solution based on finite difference modelling (FDM) with an alternating direction implicit (ADI) scheme. The layer dynamic was described with a parametric differential equation, and it was coupled to the concentrated and distributed thermal models of the PCB and the capacitor. The parameter values were determined by fitting to measured data. It was found that the heat transfer coefficient is inversely proportional to the layer thickness, and it changes over time according to the dynamic properties of layer growth. It was corroborated that the heat transfer depends on the geometry and thermal properties of the heated surfaces in VPS ovens. The presented method shows good agreement with the validation data. The new method provides a significant update over previous modelling approaches describing the condensation-based heating of the VPS process.

Study the Electrical Properties of Surface Mount Device Integrated Silver Coated Vectran Yarn.

Smart textiles have attracted huge attention due to their potential applications for ease of life. Recently, smart textiles have been produced by means of incorporation of electronic components onto/into conductive metallic yarns. The development, characterizations, and electro-mechanical testing of surface mounted electronic device (SMD) integrated E-yarns is still limited. There is a vulnerability to short circuits as non-filament conductive yarns have protruding fibers. It is important to determine the best construction method and study the factors that influence the textile properties of the base yarn. This paper investigated the effects of different external factors, namely, strain, solder pad size, temperature, abrasion, and washing on the electrical resistance of SMD integrated silver-coated Vectran (SCV) yarn. For this, a Vectran E-yarn was fabricated by integrating the SMD resistor into a SCV yarn by applying a vapor phase reflow soldering method. The results showed that the conductive gauge length, strain, overlap solder pad size, temperature, abrasion, and washing had a significant effect on the electrical resistance property of the SCV E-yarn. In addition, based on the experiment, the E-yarn made from SCV conductive thread and 68 Ω SMD resistor had the maximum electrical resistance and power of 72.16 Ω and 0.29 W per 0.31 m length. Therefore, the structure of this E-yarn is also expected to bring great benefits to manufacturing wearable conductive tracks and sensors.

Effect of different thermocouple constructions on heat-level vapour phase soldering profiles

PurposeTo improve productivity and reach better quality in assembling, measurements and proper process controlling are a necessary factor. This study aims to focus on the monitoring heat-level-based vapour phase reflow soldering (VPS), where – as it was found – different thermocouple constructions can affect the set parameters of the oven and resulting soldering profiles significantly.Design/methodology/approachThe study experiments showed significant alteration of the heating profiles during the process of the reflowing using different construction of k-type thermocouples. In a heat-level-based VPS oven, polytetrafluoroethylene (PTFE), perfluoroalkoxy (PFA) gas and water-resistant, fibreglass, thin PFA and ultrathin PFA-covered thermocouples were tested with ±1 °C precision. The oven parameters were swept according to the heating power; the length of the introduced thermocouple cables was also taken into account. An FR4-based sample PCB was used for monitoring the temperature.FindingsAccording to the results, due to the mass and volume of the thermocouples’ wires, different transients were observed on the resulting soldering profiles on the same sample PCB. The thermocouples with lower thermal mass result in faster profiles and significantly different heating factor values compared to the thermocouples that have larger thermal mass. Consequently, the length of the thermocouple wires put in the oven has also considerable effect on the heat transfer of the PCB inside the oven as well.Originality/valueThe paper shows that the thermocouple construction must be taken into account when setting up a required soldering profile, while the thermal mass of the wires might cause a significant difference in the prediction of the actual and expected soldering temperatures.

Investigating heat transfer coefficient differences on printed circuit boards during vapour phase reflow soldering

The paper presents an analysis of measuring and evaluating heat transfer coefficients for Vapour Phase Soldering (VPS) in saturated vapour for electronics assembling. The prepared Printed Circuit Board (PCB) is practically considered as a horizontal plate (rectangular or disc shaped) during the process. The novel measurement setup is optimized to minimize any perturbing effect of the instrumentation. The obtained temperature data is processed to calculate the heat transfer coefficient distribution on the boards, where the inhomogeneity of the heating is presented according to the geometry of the PCB. The differences reveal the need of careful circuit and component placement design, while the heat transfer coefficient values may considerably differ even on a simple board shape and surface during heating according to the central parts and edges-corners of the rectangular board. The effect is more emphasized on rectangle boards, however edge effect it is also observable on disc shaped boards as well. The paper also points to related design and manufacturing recommendations.

X-ray inspection and Six-Sigma in analysis of LED thermal pad coverage

PurposeThe purpose of this paper is to evaluate selected methods of reduction voidings in lead-free solder joints underneath thermal pads of light-emitting diodes (LEDs), using X-ray inspection and Six Sigma methodology.Design/methodology/approachOn the basis of cause and effect diagram for solder voiding, the potential causes of voids and influence of process variables on void formation were found. Three process variables were chosen: the type of reflow soldering, vacuum incorporation and the type of solder paste. Samples of LEDs were mounted with convection and vapour phase reflow soldering. Vacuum was incorporated into vapour phase soldering. Two types of solder pastes OM338PT and LFS-216LT were used. Algorithm incorporated into X-ray inspection system enabled to calculate the statistical distribution of LED thermal pad coverage and to find the process capability index (Cpk) of applied soldering techniques.FindingsThe evaluation of selected soldering processes of LEDs in respect of their thermal pad coverage and statistical Cpk indices is presented. Vapour-phase soldering with vacuum is capable (Cpk > 1) for OM338PT and LFS-216LT paste. Convection reflow without vacuum with LFS-216LT paste is also capable (Cpk = 1.1). Other technological soldering processes require improvements. Vacuum improves radically the capability of a reflow soldering for an LED assembly. When vacuum is not accessible, some improvement of capability to a lower extent is possible by an application of void-free solder pastes.Originality/valueSix Sigma statistical methodology combined with X-ray diagnosis was used to check whether applied methods of void reduction underneath LED thermal pads are capable processes.

Energy Efficiency Analysis of Vapor Phase Soldering Technology through Exergy-Based Metric

In electronics production, the condensation based soldering technologies are known for reproducible solder profiles and efficient heat transfer methodology. The recent advancements in lead-free soldering and requirements for absolute void-free interconnections to increase the reliability and lifetime of the product needs optimization of the soldering process. The vacuum assisted vapor phase soldering process addresses the requirements with respect to mass production and parallelly resource efficient production which is also the motivation for the present work. This study is devoted to quantify the resource consumption and qualify this consumption through exergy flows in a vacuum vapor phase reflow soldering technology in electronics manufacturing.The analysis implies on the saving potential for energy consumption specifically during the vacuum process which also defines the void reduction quality of solder joints. Exergy efficiency analysis of a temperature profile depicts the influence of the materials used in the demonstrator. Shortening the production lead‑time, and increasing the production rate increase the efficiency of exergy and prevents wastage of usable energy. Furthermore, the set-up improvements for the temperature profiles processes are necessary, and the changes toward developing new, transformational technologies in pre-heating and vacuum zones are mandatory if a high efficiency of resources used is aimed.

Moisture diffusion and heat transfer in plastic IC packages

This paper deals with finite-element (FE) simulations of moisture diffusion during preconditioning of plastic integrated circuit (IC) packages as well as the simultaneous diffusion of heat and moisture during vapor phase reflow (VPR) soldering. More realistic 2-D analyses are described. The results show good agreement with experimental data. The limitations of hitherto one-dimensional (1-D) analyses are also examined. The transient build-up of water vapor pressure in the delaminated pad-resin interface during vapor phase reflow soldering is also obtained. It is found that, irrespective of the manner of moisture preconditioning (moisture absorption or desorption), the same critical water vapor pressure level of about 1 MPa is obtained for the plastic IC package under study. It is also shown that the water vapor in the delaminated interface never reached saturation during the short period when solder is reflowed and re-solidified.

Stress‐rupture and Creep Behaviour of 63Sn‐37Pb Production Soldered Connections

Quasi shear and tensile mode stress‐rupture and quasi shear mode creep behaviours were investigated for aged production surface mount soldered connections of 127 mm pitch, rigid gullwing and J‐bend configurations at ambient and 60°C (on limited specimens) environments. These joints were manufactured by the vapour phase reflow soldering process using a 63Sn‐37Pb solder composition. Metallographic examinations and fractrographic studies were also performed on appropriate specimens to characterise the metallurgical attributes of the solder and the joint failure. A relatively coarse solder microstructure was observed with both joint configurations. The steady‐state creep data of both soldered joints exhibited two distinct creep regimes. A grain boundary‐controlled regime at low loads with a slope of 042 for gullwing and 0?50 for J‐bend joints was followed by a dislocation climb‐controlled regime at high loads with a slope of 0?13 and 0?24 for gullwing and J‐bend configurations, respectively. The log‐log plot of applied load varied linearly with rupture time for the entire load range for the respective soldered joints for both modes of testing at room temperature. A transgranular fracture morphology was found to predominate for the entire load regime for the quasi shear mode tested gullwing joints. A mixed‐mode fracture morphology with predominantly transgranular features was observed for both low and high loading conditions for quasi shear mode tested J‐bend specimens. The steady‐state creep elongation in shear showed a strong dependence on the applied load for both types of soldered joints. This was primarily attributed to the presence of relatively large creep transients, especially at higher loads.

New products

The 3M Industrial Chemical Products Group, which manufactures a selection of ‘Fluorinert’ Liquids for Vapour Phase reflow soldering, liquid reliability testing and the immersion cooling of electronic components and assemblies, has now expanded its range with the introduction of the new ‘Fluorinert’ Liquid Heat Sink.

Temperature distribution in IC plastic packages in the reflow soldering process

The temperature distribution in IC (integrated circuit) plastic packages in the reflow soldering process was investigated by both an experimental method and an analytical method. A temperature sensor composed of a p-n junction diode was embedded in a silicon chip and the chip was moulded in an actual plastic package to measure the chip temperature in the soldering process. Temperature variations of the chip during the dip-coating process, the vapour-phase reflow soldering, and the infrared reflow soldering were obtained. Finite-element method analysis was performed to develop an effective method for estimating the temperature distribution in the package. It is concluded that the combination of laboratory experiment, proper modelling of thermal boundary condition for the package, and finite-element analysis is an effective approach to find a satisfactory operative condition for a soldering process. >

Temperature Distribution in IC Plastic Packages in the Reflow Soldering Process

The temperature distribution in IC (integrated circuit) plastic packages in the reflow soldering process was investigated by both an experimental method and an analytical method. A temperature sensor composed of a p-n junction diode was embedded in a silicon chip and the chip was moulded in an actual plastic package to measure the chip temperature in the soldering process. Temperature variations of the chip during the dip-coating process, the vapour-phase reflow soldering, and the infrared reflow soldering were obtained. Finite-element method analysis was performed to develop an effective method for estimating the temperature distribution in the package. It is concluded that the combination of laboratory experiment, proper modelling of thermal boundary condition for the package, and finite-element analysis is an effective approach to find a satisfactory operative condition for a soldering process.< <ETX xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">&gt;</ETX>

Large Copper Substrates for Surface-Mounted Components

The development of large and functionally complex digital semiconductor chips operating at high clock rates has been paralleled by the elaboration of novel packaging concepts to accommodate the large number of input/output ports associated with such devices, and to permit pretesting and characterization before assembly. Probably the most successful packaging approach for such chips is the ceramic leadless chip carrier (LCC) which, in addition to the requirements listed above, provides low reactance interconnects with equal path lengths for all ports. Large substrates are used in combination with LCC's and other surfacemounted components to form the final circuit. For military and other high reliability applications, the preferred substrate material is alumina, which matches the temperature coefficient of the integrated circuit (IC) package; conductors and soldering pads are applied by thick-film screening techniques. Compared to the traditional conductor materials used in thick-film hybrid fabrication (gold, silver, platinum-gold), copper offers several advantages with respect to solderability and repairability but requires more sophisticated handling and processing techniques. Since it is a relatively new technology, performance and processing data are still sparse; nevertheless copper is now used in a number of critical military applications where the requirements for solderability, repairability, thermal conductivity, and cost could not easily be met by precious metal technology. The Raytheon Company has set up in its Quincy, Massachusetts, Plant a production facility capable of manufacturing large multilevel copper motherstrates (4 inch x 5 inch) at the rate of 400 units per month, with production expected to rise to a level of 1000 units per month by mid-1985. The 30 different designs in current production are intended to receive between 60 and 80 LCC's of various sizes and configurations mounted by vapor phase reflow soldering. As many as 12 desoldering and resoldering procedures may be carried out on each board to replace defective LCC's. Each substrate requires an average of 50 screening steps, with some designs calling for 60 or more. The number of conductor layers varies from five to seven, with as many as 2000 interconnecting vias per unit. Despite the complexity of this family of devices the overall yields have averaged 85 percent thanks to rigorous process and material controls. All procedures starting with computeraided design (CAD) artwork generation and screen manufacturing are carried out within the same plant. The circuits exhibit no bowing (potatochip effect) even without compensatory backside screening, thereby reducing final thickness and weight, and improving thermal transfer to the heat sink in the final system assembly.