Large Copper Substrates for Surface-Mounted Components

Abstract

The development of large and functionally complex digital semiconductor chips operating at high clock rates has been paralleled by the elaboration of novel packaging concepts to accommodate the large number of input/output ports associated with such devices, and to permit pretesting and characterization before assembly. Probably the most successful packaging approach for such chips is the ceramic leadless chip carrier (LCC) which, in addition to the requirements listed above, provides low reactance interconnects with equal path lengths for all ports. Large substrates are used in combination with LCC's and other surfacemounted components to form the final circuit. For military and other high reliability applications, the preferred substrate material is alumina, which matches the temperature coefficient of the integrated circuit (IC) package; conductors and soldering pads are applied by thick-film screening techniques. Compared to the traditional conductor materials used in thick-film hybrid fabrication (gold, silver, platinum-gold), copper offers several advantages with respect to solderability and repairability but requires more sophisticated handling and processing techniques. Since it is a relatively new technology, performance and processing data are still sparse; nevertheless copper is now used in a number of critical military applications where the requirements for solderability, repairability, thermal conductivity, and cost could not easily be met by precious metal technology. The Raytheon Company has set up in its Quincy, Massachusetts, Plant a production facility capable of manufacturing large multilevel copper motherstrates (4 inch x 5 inch) at the rate of 400 units per month, with production expected to rise to a level of 1000 units per month by mid-1985. The 30 different designs in current production are intended to receive between 60 and 80 LCC's of various sizes and configurations mounted by vapor phase reflow soldering. As many as 12 desoldering and resoldering procedures may be carried out on each board to replace defective LCC's. Each substrate requires an average of 50 screening steps, with some designs calling for 60 or more. The number of conductor layers varies from five to seven, with as many as 2000 interconnecting vias per unit. Despite the complexity of this family of devices the overall yields have averaged 85 percent thanks to rigorous process and material controls. All procedures starting with computeraided design (CAD) artwork generation and screen manufacturing are carried out within the same plant. The circuits exhibit no bowing (potatochip effect) even without compensatory backside screening, thereby reducing final thickness and weight, and improving thermal transfer to the heat sink in the final system assembly.