Vapor Phase Etching Research Articles

Enhanced Cl2 sensitivity of cobalt-phthalocyanine film by utilizing a porous nanostructured surface fabricated on glass

We demonstrate a very simple and effective approach to improve the sensitivity and the low detection limit of cobalt phthalocyanine films towards the detection of chlorine by creating a porous nanostructured surface on a glass substrate via a vapor phase etching process.

Fabrication of high aspect ratio broadband antireflection porous nano-network on glass using candle soot as a sacrificial layer for solar energy utilization

In this paper, we report the fabrication of broadband antireflection porous nano-network on the glass substrate using the combination of candle soot and HF-based vapor phase etching method. Candle soot layer plays a key role to control the pore size during the etching process. Field emission electron microscopy results showed that the pores have the tapering profile, and the pores size was restricted to the sub-wavelength dimension. Therefore, an excellent broadband antireflection with an enhancement of ∼7% in the maximum total transmittance as compared to plain glass has been achieved. Moreover, reflectance from the etched surface remains quite low (<4%) over a broad range of incident angles up to 58°. The broadband antireflection property was further examined by finite difference time domain simulation. Further, we demonstrate a relative improvement of ∼6% in the Jsc (ΔJsc/Jsc) of solar cell covered with the etched glass.

(Invited) Epitaxial Transition Metal Nitrides for III-Nitride Devices: Application for Epitaxial Lift-Off and Transfer

Integration of epitaxial metallic layers within a semiconductor device structure has long been desired for a variety of applications; however, the practical realization of this goal has remained elusive. We have recently demonstrated the epitaxial growth of a transition metal nitride, Nb2N, on 6H-SiC substrates using plasma-assisted molecular beam epitaxy [1]. The films, ranging from 4 to 100 nm in thickness, exhibited single phase, sub-nm rms roughness, and low resistivity. Furthermore, high quality III-nitride layers can be grown on the Nb2N/SiC templates, either in a continuous growth run or after removing and re-loading the Nb2N/SiC template [2], without observable reaction between any of the layers. III-nitride material quality has been verified by growing a high-electron-mobility transistor (HEMT) device structure on a Nb2N/SiC template, achieving a two-dimensional electron gas (2DEG) mobility of 1400 cm2/V-s, a sheet carrier density of 1.2x1013 cm-2, and a maximum drain current in excess of 1 A/mm [3]. One unique application of this HEMT/Nb2N/SiC structure is utilizing the Nb2N layer as a sacrificial release layer for HEMT lift-off and transfer to alternative substrates of interest [4]. We have found that the intact HEMT structure can be released from the substrate without observable degradation of the 2DEG electrical properties by selective etching of the buried Nb2N layer using XeF2 vapor phase etching [3]. This process opens the door for the integration of GaN devices with various other technological platforms (heterogeneous integration) or onto alternative substrates such as plastic or diamond. Additionally, this process could allow for the reuse of SiC substrates after device lift-off. This presentation will focus on the materials development of epitaxial Nb2N layers and their use as a sacrificial release layer for III-nitride device transfer from SiC substrates. [1] D.S. Katzer et al., Appl. Phys. Express, vol. 8, no. 8, 085501 (2015). [2] N. Nepal et al., Appl. Phys. Express, vol. 9, no. 2, 021003 (2016). [3] D.J. Meyer et al., CS MANTECH Conference, May 16 – 19, Miami, USA (2016). [4] D.J. Meyer and B.P. Downey, “Lift-off of epitaxial layers from silicon carbide or compound semiconductor substrates,” US patent application no. 14/331,440. PCT application no. PCT/US14/46609.

Cathodoluminescence study on the impurity behaviors at threading dislocations in GaN

The threading dislocations in GaN provide diffusion routes for impurity incorporation, which substantially influences GaN based optoelectronic devices. Here, we investigated the characteristics of the impurity incorporation at threading dislocations by HCl vapor phase etching and cathodoluminescence (CL) measurements. The distinctive etch pits induced by HCl vapor phase etching correspond definitely to different types of dislocations, and the etching process causes simultaneously H incorporation at a high temperature. CL spectra of the etch pits were analyzed, and the observed difference in the redshift of near band emission peak indicates that mix dislocations are more favorable for impurity incorporations than that of edge dislocations. The understanding on the impurity incorporation behavior at threading dislocations helps to obtain high quality GaN nanostructures.

Parallel preparation of plan-view transmission electron microscopy specimens by vapor-phase etching with integrated etch stops

Specimen preparation remains a practical challenge in transmission electron microscopy and frequently limits the quality of structural and chemical characterization data obtained. Prevailing methods for thinning of specimens to electron transparency are serial in nature, time consuming, and prone to producing artifacts and specimen failure. This work presents an alternative method for the preparation of plan-view specimens using isotropic vapor-phase etching with integrated etch stops. An ultrathin amorphous etch-stop layer simultaneously serves as an electron transparent support membrane whose thickness is defined by a controlled growth process such as atomic layer deposition with sub-nanometer precision. This approach eliminates the need for mechanical polishing or ion milling to achieve electron transparency, and reduces the occurrence of preparation induced artifacts. Furthermore, multiple specimens from a plurality of samples can be thinned in parallel due to high selectivity of the vapor-phase etching process. These features enable dramatic reductions in preparation time and cost without sacrificing specimen quality and provide advantages over wet etching techniques. Finally, we demonstrate a platform for high-throughput transmission electron microscopy of plan-view specimens by combining the parallel preparation capabilities of vapor-phase etching with wafer-scale micro- and nanofabrication.

Extraordinary high broadband specular transmittance of sodalime glass substrate by vapor phase etching

In this paper, we present a simple method to fabricate the antireflective porous surface on sodalime glass using a single step HF-vapor phase etching method. Under optimal conditions, both-sides etched glass substrate exhibited a broadband enhancement in the transmittance with maximum transmittance as high as 99.2% at ∼500nm with extremely low diffusive scattering. The measured transmittance exceeds by ∼7.6% as compared to plain glass (91.6%). X-ray photoelectron spectroscopy results confirmed the formation of a fluoride layer comprising of NaF and CaF2 on sodalime glass substrate after etching. Field emission scanning electron microscopy results showed the formation of porous structure with randomly distributed pores of size <150nm. The refractive index of the porous fluoride layer was found to be 1.28 and lowest reflectance of 0.6% has been achieved. Moreover, reflection (measured at 500nm) remains below 1.5% over a range of incident angles (8–48°), which is ascribed to the fact that refractive index follows a gradual change in the nanoporous surface. The theoretical transmittance of the optimized etched glass determined by finite difference time domain simulation shows a good agreement with the experimental results. The silicon solar cell covered with both-sides optimized etched glass showed a relative increase of ∼4% in power conversion efficiency as compared to a solar cell covered with a plain glass.

Broadband quasi-omnidirectional sub-wavelength nanoporous antireflecting surfaces on glass substrate for solar energy harvesting applications

A cost effective, facile and scalable method to fabricate the stable broadband antireflective (AR) surface on glass substrates for solar energy applications is still a challenge. In this paper, we have demonstrated a simple and non-lithographic method to fabricate the broadband quasi-omnidirectional AR nanoporous surface on glass substrates by hydrofluoric (HF) acid based vapor phase etching method. Both-sides etched sodalime glass substrate under optimized conditions showed broadband enhanced transmittance with maximum total transmittance of ~97% at 598nm. The measured transmittance exceeds by ~5.4% as compared to plain glass (91.6%). Field emission scanning electron microscopy results showed that an AR nanoporous surface with graded porosity was formed on sodalime glass substrate after etching. Due to the graded porosity, the fabricated nanoporous surface on sodalime glass substrate showed excellent broadband enhanced transmittance, and exhibited low reflectance <2.8% over a wide range of incidence angles (8–48°). The mechanism of nanostructured surface formation and the effect of etching parameters on transmittance have been discussed in detail. To get more insight, the theoretical transmittance of the optimized sample has been determined by finite difference time domain simulation, which confirms a good agreement of AR property with the experimental results. Furthermore, these AR nanoporous surface showed good adhesion property, excellent thermal and chemical stability, and exhibited outstanding stability against outdoor exposure. These properties signify its strong potential in various solar energy devices.

Pixel-Parallel 3-D Integrated CMOS Image Sensors With Pulse Frequency Modulation A/D Converters Developed by Direct Bonding of SOI Layers

We have developed for the first time a 3-D integrated CMOS image sensor with pixel-parallel analog-to-digital converters (ADCs). Photodiode (PD) and inverter layers are prepared on separate silicon-on-insulator layers and directly bonded with damascened Au electrodes. The handle layer is then removed by grinding and XeF2 vapor phase etching to expose the PD surface. The developed process is suitable for pixelwise interconnection because it allows the damascened Au electrodes to be 1 $\mu \text{m}$ in diameter or less. An ADC circuit is designed based on pulse frequency modulation where pulses are generated proportional to the illumination intensity, and contains a PD, inverters, a reset transistor, and counters. A prototype 3-D integrated CMOS image sensor is also developed with 64 pixels, which acquires video images without pixel defects. A wide dynamic range of >80 dB is confirmed for the incident light intensity. The experimental results demonstrate the feasibility of pixel-level 3-D integration for high-performance CMOS image sensors.

Defect reduction in GaN regrown on hexagonal mask structure by facet assisted lateral overgrowth

It is demonstrated that the threading dislocation density in GaN is considerably reduced by Facet Assisted Epitaxial Lateral Overgrowth (FACELO) on a hexagonal honeycomb grid structure. We observed a more isotropic strain and curvature development in the GaN layer by such a mask geometry. Here, we describe how to achieve a nearly dislocation-free surface by a fairly complex variation of the epitaxial growth parameters. Eventually, dislocation analysis of epitaxially grown GaN using an HCl vapor phase etching process resulted in dislocation densities below 106cm−2.

Lateral Gemanium Growth for Local GeOI Fabrication

High quality local Germanium-on-oxide (GeOI) wafers are fabricated using selective lateral germanium (Ge) growth technique by a single wafer reduced pressure chemical vapor deposition system. Mesa structures of 300 nm thick epitaxial silicon (Si) interposed by SiO2 cap and buried oxide are prepared. HCl vapor phase etching of Si is performed prior to selective Ge growth to remove a part of the epitaxial Si to form cavity under the mesa. By following selective Ge growth, the cavity was filled. Cross section TEM shows dislocations of Ge which are located near Si / Ge interface only. This mechanism is similar to aspect-ratio-trapping but here we are using a horizontal approach, which offers the option to remove the defective areas by standard structuring techniques. By plan view TEM it is shown, that the dislocations in Ge which direct to SiO2 cap or to buried-oxide (BOX) are located near the interface of Si and Ge. The dislocations which run parallel to BOX are observed only in [110] or equivalent direction. The resulting Ge grown toward [010] direction contains no dislocations. A root mean square of roughness of ~0.2 nm is obtained after the SiO2 cap removal. Tensile strain in the Ge layer is observed due to higher thermal expansion coefficient of Ge compared to Si and SiO2.

Three-dimensional, flexible graphene bioelectronics.

We report 3-dimensional (3D) graphene-based biosensors fabricated via 3D transfer of monolithic graphene-graphite structures. This mechanically flexible all-carbon structure is a prospective candidate for intimate 3D interfacing with biological systems. Monolithic graphene-graphite structures were synthesized using low pressure chemical vapor deposition (LPCVD) process relying on the heterostructured metal catalyst layers. Nonplanar substrates and wet-transfer method were used with a thin Au film as a transfer layer to achieve the 3D graphene structure. Instead of the typical wet-etching method, vapor-phase etching was performed to minimize the delamination of the graphene while removing the transfer layer. We believe that the monolithic graphene-graphite synthesis combined with the conformal 3D transfer will pave the way for the 3D conformal sensing capability as well as the intracellular recording of living cells in the future.

Selective Lateral Germanium Growth for Local GeOI Fabrication

High quality local Germanium-on-oxide (GeOI) wafers are fabricated using selective lateral germanium (Ge) growth technique by a single wafer reduced pressure chemical vapor deposition system. Mesa structures of 300 nm thick epitaxial silicon (Si) interposed by SiO2 cap and buried oxide are prepared. HCl vapor phase etching of Si is performed prior to selective Ge growth to remove a part of the epitaxial Si to form cavity under the mesa. By following selective Ge growth, the cavity was filled. Cross section TEM shows dislocations of Ge which are located near Si / Ge interface only. By plan view TEM, it is shown that the dislocations in Ge which direct to SiO2 cap or to buried-oxide (BOX) are located near the interface of Si and Ge. The dislocations which run parallel to BOX are observed only in [110] and [1–10] direction resulting Ge grown toward [010] direction contains no dislocations. This mechanism is similar to aspect-ratio-trapping but here we are using a horizontal approach, which offers the option to remove the defective areas by standard structuring techniques. A root mean square of roughness of ∼0.2 nm is obtained after the SiO2 cap removal. Tensile strain in the Ge layer is observed due to higher thermal expansion coefficient of Ge compared to Si and SiO2.

Toward highly radiative white light emitting nanostructures: a new approach to dislocation-eliminated GaN/InGaN core-shell nanostructures with a negligible polarization field.

White light emitting InGaN nanostructures hold a key position in future solid-state lighting applications. Although many suggested approaches to form group III-nitride vertical structures have been reported, more practical and cost effective methods are still needed. Here, we present a new approach to GaN/InGaN core-shell nanostructures at a wafer level formed by chemical vapor-phase etching and metal-organic chemical vapor deposition. Without a patterning process, we successfully obtained high quality and polarization field minimized In-rich GaN/InGaN core-shell nanostructures. The various quantum well thicknesses and the multi-facets of the obelisk-shaped core-shell nanostructures provide a broad spectrum of the entire visible range without changing the InGaN growth temperature. Due to their high crystal quality and polarization field reduction, the core-shell InGaN quantum wells show an ultrafast radiative recombination time of less than 200 ps and uniformly high internal quantum efficiency in the broad spectral range. We also investigated the important role of polarization fields in the complex recombination dynamics in InGaN quantum wells.

A dicing free SOI process for MEMS devices

This paper presents a full wafer, dicing free, dry release process for MEMS silicon-on-insulator (SOI) sensors and actuators. The developed process is particularly useful for inertial sensors that benefit from a large proof mass, for example accelerometers and gyroscopes. It involves consecutive front and backside deep reactive ion etching (DRIE) of the substrate to define the device features, release holes, and trenches. This is followed by hydrofluoric acid vapor phase etching (HF VPE) to release the proof mass and the handle wafer underneath to allow vertical displacements of the proof mass. The release process also allows the devices to be detached from each other and the substrate without the need of an extra dicing step that may damage the delicate device features or create debris. In the work described here, the process is demonstrated for the full wafer release of a high performance accelerometer with a large proof mass measuring 4x7mm^2. The sensor was successfully fabricated with a yield of over 95%.

Dislocation-Eliminating Chemical Control Method for High-Efficiency GaN-Based Light Emitting Nanostructures

A dislocation-eliminating chemical control method for high-quality GaN nanostructures together with various types of InGaN quantum well structures are demonstrated using a chemical vapor-phase etching technique. Unlike chemical wet etching, chemical vapor-phase etching could efficiently control the GaN and form various shapes of dislocation-free and strain-relaxed GaN nanostructures. The chemically controlled GaN nanostructures showed improved crystal quality due to the selective etching of defects and revealed various facets with reduced residual strain via the facet-selective etching mechanism. These structural properties derived excellent optical performance of the GaN nanostructures. The chemical vapor-phase etching method also showed possibilities of the fascinating applications for high-efficiency InGaN quantum well structures, such as InGaN quantum well layer on void embedded GaN layer, InGaN quantum well embedded GaN nanostructure, and InGaN/GaN core/shell nanostructure.

A Highly Sensitive Determination of Bulk Cu and Ni in Heavily Boron-doped Silicon Wafers

The new metrology, Advanced Poly-silicon Ultra-Trace Profiling (APUTP), was developed for measuring bulk Cu and Ni in heavily boron-doped silicon wafers. A Ni recovery yield of 98.8% and a Cu recovery yield of 96.0% were achieved by optimizing the vapor phase etching and the wafer surface scanning conditions, following capture of Cu and Ni by the poly-silicon layer. A lower limit of detection (LOD) than previous techniques could be achieved using the mixture vapor etching method. This method can be used to indicate the amount of Cu and Ni resulting from bulk contamination in heavily boron-doped silicon wafers during wafer manufacturing. It was found that a higher degree of bulk Ni contamination arose during alkaline etching of heavily boron-doped silicon wafers compared with lightly boron-doped silicon wafers. In addition, it was proven that bulk Cu contamination was easily introduced in the heavily boron-doped silicon wafer by polishing the wafer with a slurry containing Cu in the presence of amine additives.

Epitaxial growth of Si:C/Si/SiGe into cavity formed by selective etching of SiGe

Epitaxial growth of Si:C, Si or SiGe in the cavity formed by selective vapor phase etching of sacrificial SiGe layer by HCl using a RPCVD system was investigated. The sacrificial SiGe layer was etched with very high selectivity. Epitaxial Si was deposited into the selectively etched cavity by non-selective and selective deposition processes. Weak strain contrast was observed by TEM at the interface where the growthfronts from top and bottom of the cavity were meeting each other. No or weak strain contrast was observed in the Si cap layer at middle to shallow part of the cavity. By non-selective SiGe growth, the SiGe layer was deposited on the Si cap layer only. The Si cap layer on the cavity seems to be bended and pressed down in the early stage of non-selective SiGe growth. On the other hand, in the case of selective SiGe growth, the cavity was filled. Strain contrast was observed by TEM in the Si cap layer on selectively grown SiGe. Bending of Si cap layer after selective SiGe growth was increased with increasing Ge concentration, indicating that tensile strain was generated by SiGe growth in the cavity.

A Novel Vapor Phase Etching Process for Si

A Novel Vapor Phase Etching Process for Si

Selective vapor phase etching of SiGe versus Si by HCl

Chemical vapor phase etching of SiGe versus Si by HCl was investigated using a single wafer reduced pressure CVD (RPCVD) system. The etch rate of SiGe layer was higher than that of Si and it is increasing with increasing Ge concentration, that means selectivity of etch rate of SiGe to Si is increasing with increasing Ge concentration. The etching process of Si seems to be anisotropic because etching of [110] direction was observed whereas the etching of [100] direction was negligible. Activation energy of etch rate of Si and SiGe with 10, 20 and 30% were estimated to ~ 2.1 eV (~ 48 kcal/mol). The combination of differential Si/SiGe growth, selective polycrystalline Si/SiGe etching and epitaxial SiGe etching in one process was demonstrated.

Selective vapor phase etching of SiGe by HCl in a RPCVD reactor

Chemical vapor phase etching of epitaxial SiGe by HCl was investigated using a single wafer reduced pressure CVD (RPCVD) system. For the sample preparation, patterning and dry etching were performed on the Si substrate with SiGe buried layers to open the sidewalls of the buried SiGe layers. The etchrate of the lateral direction was measured. The etchrate of SiGe is increasing with increasing SiGe thickness saturating at SiGe thicknesses higher than ∼25 nm. This result could be caused by diffusion effects of molecules in the narrow trenches during the etching. At the same SiGe thickness, the etchrate of SiGe is increasing with increasing etching temperature. B doping does not affect the etchrate of SiGe. P doping is increasing and C doping is decreasing the etchrate. Facet formation of the etchfront of Si and SiGe depends on initial surface orientation. These results enable improved process controllability of the etching process using doped layers for different applications.