Threshold Voltage Values Research Articles

Physical understanding of a normally off p-GaN/AlGaN/GaN HEMT gate stack and a review of VTH measurement techniques

Abstract In this report a comprehensive review of the variations in threshold voltage (VTH) resulting from diverse VTH measurement bias conditions employed by leading manufacturers, as well as VTH extraction techniques is made. Notably, a standard deviation of 15% is observed in threshold voltage values due to variations in measurement bias conditions. This variation is attributed to the change in the lateral electic field conditions across gate and drain which occurs due to the change in bias conditions. Additionally, a simplified physical interpretation of the gate stack in p-GaN gate normally-off AlGaN/GaN on Si HEMTs is made. The formation of the two-dimensional electron gas (2DEG), the charge balance within the pGaN/AlGaN/GaN gate stack, and an analytical expression for threshold voltage are examined. Furthermore, various trapping mechanisms within the gate stack are reviewed to comprehend the dynamic conditions potentially contributing to threshold voltage instability during nominal operation.

Rotaxane Based Molecular Junctions Have Emerged as Promising Components For Electronic and Optoelectronic Applications

Background: Rotaxane molecule consists of three main parts: wheel, axle, and stoppers. This study was conducted to increase the number of wheels to get the electronic, electrical and thermal properties of Nano molecular junctions based on rotaxane. Materials and Methods: Calculations were performed to evaluate the transport properties and the geometrically optimization of these molecular junctions using a combination of DFT, SIESTA code, Gollum code and a non-equilibrium Green’s function formalism. Each molecule was attached to opposing 35-atom (111) directed pyramidal gold electrodes. DFT and GGA were used to compute the ground state energy of various molecular junctions. Results: The results of the T(E) showed high values, and this is evidence of that constructive interference that is controlled and reinforced by changing the number of wheels in the rotaxane molecules, which affected the HOMO-LUMO gap and thus contributed to raising or lowering the T(E) values. The relationship between G/Go and thermopower showed that the highest G/Go yields to low thermopower. The decay constant is a fundamental property that influences the transmission of electrons, conductance properties, and threshold voltage in the rotaxane molecules. Conclusion: Molecular junctions based on Rotaxane showed high values of the T(E), which increase the electrical conductivity, making them promising for electronic applications. The smaller value of threshold voltage is a useful property for different applications. The results of power factor bring to us an important conclusion, which is that the impact of G/G0 is more dominant than that of thermopower in the case of rotaxane molecular junctions.

Enhancement-mode ZnGa2O4-based Phototransistor with high UV–visible rejection ratio grown by metalorganic chemical vapor deposition

In this study, a high-crystallinity zinc gallium oxide (ZnGa2O4) epilayer of about 80 nm thickness was successfully grown using metalorganic chemical vapor deposition. X-ray diffraction, atomic force microscopy, UV–visible spectroscopy measurements, and X-ray photoelectron spectroscopy were used to investigate the quality of the epilayer. Transmission line measurement analysis revealed the electrical properties of the ZnGa2O4 epilayer: a sheet resistance of 276 MΩ/□, a transfer length of 0.28 μm, and a specific contact resistivity of 21.63 Ω/mm2. A phototransistor made of ZnGa2O4 was designed with a channel width of 250 μm and a channel length of 20 μm. The source-drain electrodes were fabricated using a Ti/Al/Ni stacking technique. The gate dielectric comprised 30 nm thick Al2O3, and the gate contact was made of Ni. The device possessed a higher threshold voltage value of about 4.8 V and an impressive On/Off current ratio of 106. Under 240 nm UV light exposure, the phototransistor exhibited a transition from enhancement mode to depletion mode, leading to a remarkable shift in the threshold voltage from 5 V to approximately −16 V. Moreover, the responsivity and rejection ratio at 240 nm was 128.5 A/W and 105 at a gate voltage of −10 V. The study shows that an increasing thickness of the ZnGa2O4 epilayer from 80 nm to 135 nm results in a depletion mode transistor. The higher concentration of about twenty percent oxygen vacancies resulted in a longer fall time for the phototransistor. These results underscore the significant potential of ZnGa2O4 in facilitating deep UV-based detection applications.

Review of Carbon Nanotube Field Effect Transistor for Nanoscale Regime

Background: The need for high performance, small size, low delay, low power consumption, and long battery backup of portable systems is increasing with the advancement of technology. Many features of portable systems can be improved using scaling methods. In the scaling process, reducing the size of devices causes serious difficulties, including the short channel effect (SCE) and leakage current, which degenerates the characteristics of the systems. Objective: In this review paper, a trending carbon nanotube field effect transistor (CNTFET) technology is discussed in detail. CNTFET can replace the conventional metal oxide semiconductor field effect transistor (MOSFET) technology to overcome the SCE problems in the nanoscale regime and also meet the requirements of portable systems. Methods: The CNTFET is an extremely good nanoscale technology due to its one-dimension band structure, high transconductance, high electron mobility, superior control over channel formation, and better threshold voltage. This technology is used to construct high-performance and low-power circuits by replacing the MOSFET technology. CNTFET in comparison to MOSFET takes the carbon nanotube (CNT) as a channel region. Results: The value of threshold voltage in CNTFET changes with the diameter of CNT. The threshold voltage of the devices controls many parameters at the circuit-level design. Hence, the detailed operation and the characteristics of CNTFET devices are presented in this review paper. The existing CNTFET-based ternary full adder (TFA) circuits are also described in this review paper for the performance evaluation of different parameters. Conclusion: CNTFET technology is the possible solution for the SCE in the nanoscale regime and is capable to design efficient logic circuits. The circuits using the CNTFET technology can provide better performance and various advantages, including fast speed, small area, and low power consumption, in comparison to the MOSFET circuits. Thus, CNTFET technology is the best choice for circuit designs at the nanoscale.

Gate-Oxide Degradation Monitoring of SiC MOSFETs Based on Transfer Characteristic With Temperature Compensation

Gate-oxide degradation is a concern in SiC MOSFETs especially in safety critical applications such as aerospace and electric vehicles (EV). To address this concern, this paper presents an accurate gate-oxide degradation monitoring solution based on the SiC devices’ transfer characteristics. Specifically, a plug-in circuit for gate driver is proposed to extract the transconductance ( <italic xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">g_m</i> ) and threshold voltage ( <italic xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">V_th</i> ) values from transfer characteristic. By using the threshold voltage as gate-oxide aging reference and transconductance as the junction temperature reference, the two precursors are combined to obtain a temperature and package degradation independent estimate of the gate-oxide health. High-temperature gate bias (HTGB) and DC power cycling tests are used to confirm <italic xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">g_m</i> ’s sensitivity to gate-oxide degradation and insensitivity to package degradation in kelvin-sourced discrete SiC MOSFETs. A simple circuit is proposed for on-board <italic xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">g_m</i> measurement using the voltage drop on the common source inductance of the MOSFET. The measured <italic xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">g_m</i> is converted into digital pulse width, which can be easily measured using a microcontroller. A comprehensive comparison is presented to demonstrate the merits of the proposed method. Lastly, the accuracy and sensitivity of temperature and aging measurements using the proposed method is validated experimentally.

Investigation of Indium doped Se-Te bulk chalcogenide glasses for electrical switching and phase changing applications

Recently, Metal-doped Se-Te chalcogenides have gained a lot of interest due to their unique capacity for electrical switching, which makes them desirable for electronic applications. This study examines the electrical switching characteristics of bulk Se86−xTe14Inx (0 ≤ x ≤ 6) amorphous alloys produced by the conventional melt-mix-quench process. The samples with an Indium atomic percentage between 2 to 6 exhibited a remarkable transition from a highly resistive to a low resistive state when subjected to an electric field with a current of 1 mA, displaying quick and reversible switching behaviour. The threshold voltage (Vth) significantly dropped from 410.6 V to 49.2 V with an increase in Indium concentration. Additionally, above the specific current threshold, these bulk glasses demonstrated memory-type switching, demonstrating their potential for data storage applications. To comprehend the trend of glass forming ability, thermal stability range and Hruby’s glass stability parameters, with their compositional dependency, Differential Scanning Calorimetry (DSC) was utilized. The sample Se80Te14In6 emerged to be the fastest phase-changing material, with a memory switching current threshold of Ith = 1.3 mA and a threshold voltage value of 49.2 V. To study the formation of crystallites in Se-Te-In alloy, X-ray diffraction patterns of pristine glass and the annealed sample were examined. Furthermore, temperature-dependent conductivity investigations showed a sharp rise in conductivity once the process crystallization begins (Tx), and also the threshold voltage (Vth) of the samples decreased linearly with rising temperature. Overall, this study provides valuable insights into the electrical switching behaviour and thermal properties of Se-Te-In chalcogenide glasses, enhancing their suitability in electronic devices.

Non-isothermal crystallization kinetics and memory switching properties of Tl-Se-Ge-Sb chalcogenide semiconductor alloy for thermally stable phase change memory applications

Quaternary (Tl20Se70Ge10)0.85Sb0.15 chalcogenide glass was synthesized using melt-quenching and thermal evaporation techniques for bulk and thin film samples, and its amorphous character was confirmed by XRD. Based on different models of non-isothermal crystallization kinetics, the average values of the glass transition and the crystallization activation energies are 121.33 and 82.94 kJ mol−1, respectively. The crystallization mechanism in the examined composition is 2D nucleation growth, according to Avrami exponent Thermal parameters of the studied quaternary glass, like fragility fluctuation free volume reduced glass transition temperature thermal stability and glass formation ability were investigated and indicated that the (Tl20Se70Ge10)0.85Sb0.15 ChG exhibits a good ability of glass formation and thermal stability. The obtained results of the dc electrical conductivity are found to increase with temperature and decrease with film thickness. The electrical conduction activation energy (0.583 ± 0.004 eV) is thickness independent and the predominant conduction mechanism is the hopping of charge carriers in the band tail localized states. The () curves of (Tl20Se70Ge10)0.85Sb0.15 chalcogenide glass film samples were analyzed and shown to be appropriate for a memory switch. The mean value of the threshold voltage decreases exponentially as temperature increases, whereas it increases linearly as film thickness increases. The values of threshold voltage and threshold resistance activation energies are 0.282 ± 0.003 and 0.521 ± 0.004 eV, respectively. The obtained switching characteristics data were discussed in view of the electrothermal model motivated by current channel Joule heating. These findings highlight the suitability of the investigated composition for various optoelectronic applications, such as memory switching devices, optical data storage, phase-change memories and optical fibres sensing devices.

Performance optimization of high-K GAA-PZT negative capacitance FET MFIS silicon nanowire for low power RFIC and analog applications

In this article, Gate-All-Around Lead Zirconate Titanate Negative Capacitance (GAA PZT- NCFET) based Silicon Nanowire (SiNW) device architecture is investigated for the RF/Analog applications using Sentauras TCAD simulations. In this study the variation of ferroelectric layer thicknesses (tfe) has been systematically investigated. The proposed device yields higher values of on current, transconductance, cut off frequency, TFP, and Ion/Ioff ratio and lower values of off current, SS and threshold voltage, compared to baseline device. The proposed device delivers Ion, gm, fT, and TFP as 3.38 mA, 9.6 mS, 7.625 THz, and 74.85 THz V−1, respectively which are 220%, 219%, 95% and 259% respectively, higher than the baseline device. Moreover, the Ion/Ioff ratio for the proposed work is 8 × 1013 which is 7.1 × 103 times that of baseline device showing a monumental increment in this ratio. Furthermore, the effect of FE thicknesses on various linearity parameters, higher order harmonics, voltage intercept points (VIP2, VIP3), third order power intercept (IIP3) and third order intermodulation distortion (IMD3) have been investigated thoroughly. The proposed device structure offers lower values of higher order harmonics and higher values of voltage intercept points. Also, the IIP3 and IMD3 have been improved. Therefore, the linearity parameters of the device have been significantly improved when compared to the baseline device. The alluring results have been utilized to optimize the bias point of the presented device. Owing to the improved RF/Analog and linearity performance, the presented device could be utilized for imminent next generation low power RFIC applications.

An unbalanced ternary multiplier cell based on graphene nanoribbon field-effect transistors for PVT-tolerant low-energy portable applications

The potential benefits of using multiple-valued logic (MVL), especially ternary logic, which includes less interconnections, quicker response times, and smaller chip sizes, has gained the interest of designers of digital systems. A practical solution for achieving circuits with multiple thresholds in an efficient manner is through using graphene nanoribbon field-effect transistors (GNRFETs) that have modifiable threshold voltage values by adjusting the width of graphene nanoribbon. This article leverages the unique characteristics of GNRFETs and proposes a new design for a single-trit ternary multiplier (TMUL) circuit. The proposed TMUL uses two supply voltages to block direct current paths from high-to-low voltage levels, resulting in power and energy savings. Additionally, unary operators such as negative and positive ternary inverters and the complement of decisive literal are used to reduce transistor count and improve circuit performance. To thoroughly evaluate the performance of the proposed GNRFET-based TMUL circuit, extensive simulations are performed using Synopsis HSPICE tool and 32-nm channel length GNRFET devices, while taking into account the influences of process-voltage-temperature variations (PVT). The simulation results confirm the robustness and reliability of the proposed design, exhibiting reductions in power consumption by 71.18% to 76.36%, and energy consumption by 67.78% to 86.54%, when compared to other state-of-the-art TMUL circuits available in literature. Moreover, Monte-Carlo simulations have been performed to demonstrate that the suggested design exhibits reduced sensitivity towards significant process variations. As a result, the presented TMUL design can be a good choice for use in low-energy battery-operated portable multimedia device.

Nanosheet Field Effect Transistor Device and Circuit Aspects for Future Technology Nodes

Moore’s law states that the technical innovations are being absorbed already. The device’s controllability has dramatically improved since moving from a straightforward MOSFET constructed with a single control gate to one with many control gates. In this research paper, the device-level simulation of vertically stacked GAA nanosheet FET is performed, for which the various geometrical variations are calibrated. This research paper examines the impact of these geometrical variations on the device’s performance. The most prominent parameters like I ON, I OFF, SS, DIBL, switching ratio, and Threshold voltage values are analyzed. For the device to be considered to have better performance I ON should be maximum, I OFF should be minimum. Hence to obtain this the thickness of the nanosheet is varied on the scale of 5 nm to 9 nm, and the width is varied from 10 nm to 50 nm. The device simulation and analysis are performed using the Visual TCAD−3D Cogenda tool.

Improving Indoor Occupancy Detection Accuracy of the SLEEPIR Sensor Using LSTM Models

We recently developed a synchronized low energy electronically chopped passive infrared (SLEEPIR) sensor node to detect stationary and moving occupants. It uses a liquid crystal shutter to modulate the infrared signal received by a traditional passive infrared (PIR) sensor and thus enables its capability to detect stationary occupants. However, the detection accuracy of the SLEEPIR sensor can be easily influenced by infrared environmental disturbances. To address this problem, in this paper, we propose two Long Short-Term Memory (LSTM) models to filter infrared environmental disturbance, named baseline LSTM (Base.LSTM) and statistical LSTM (Stat.LSTM). They use the sensor node raw output and statistical features as their respective input. For comparison, we propose two other models: the occupancy state switch detection (SSD) algorithm that directly uses a predetermined threshold voltage value to classify the occupancy state and its status change; and the multi-layer perception (MLP) classifier with statistical feature inputs (Stat.ML). To validate their detection performance, we designed two testing scenarios in different environment settings: (i) Daily occupancy tests and (ii) EDGE case tests. The first scenario intends to restore complex real-life environmental situations as much as possible in the lab and apartment rooms. The second scenario aims to verify their detection accuracy under different environmental temperatures. This scenario also considers different occupancy postures, such as lying down. Experimental results show that the detection accuracy of both LSTM models (> 95%) in both testing scenarios outperforms that of the SSD (around 82% to 94%) and the Stat.ML(around 80% to 90%).

Electromyographic signals and the starting threshold voltage of orbicularis oris muscle in healthy rhesus monkeys

Objective: To investigate the characteristics of electromyography (EMG) signals and the starting threshold voltages of the orbicularis oris muscles (OOM) in healthy rhesus monkeys under different muscle movement conditions. Methods: The EMG signals and the starting threshold voltages at different time points in 4 healthy rhesus monkeys were acquired and recorded with EMG device and evoked potentiometer. The voltage amplitude variation of EMG signals was analyzed, and the voltage amplitude range of EMG signals at the beginning of OOM contraction was established. The data were statistically analyzed by one-way ANOVA. Results: The EMG of OOM in healthy monkeys in the quiet, natural and continuous mouth-closed state was linear and relatively stable, and the absolute value fluctuated between 15 and 50 μV. The EMG waveform increased rapidly during the natural lip contraction movement, and its amplitude fluctuated greatly, with the highest absolute value of the peak value reaching hundreds of microvolts. The amplitude of EMG induced by continuous mouth closure was more than thousands of microvolts. There was no significant difference in EMG amplitudes of OOM in the healthy rhesus monkey under quiet and continuous lip closure at different time points (P>0.05). There was no significant difference in threshold voltages in the state of natural lip contraction of bilateral OOM at different time points (average range: 57.17-57.47 μV) in the healthy rhesus monkeys (P>0.05). There was no significant difference in threshold voltages of OOM induced by bilateral OOM at different time points(average range: 55.38-55.99 μV) in the healthy rhesus monkeys(P>0.05). There were significant differences in the absolute values of EMG amplitudes of OOM between the three lip movement modes: (30.67±8.72) μV in quiet and natural continuous lip closure (475.12±54.72) μV in natural lip contraction, and (921.22±312.79) μV in the induced persistent lip closure, with t values of -8.48, -9.35 and -5.01 respectively, all P<0.001. Conclusions: The EMG signals of OOM show different characteristics under different muscle movement conditions, which can be used as a basis for computer to judge and recognize the movement conditions of OOM. The upper limits of the EMG threshold voltage values of OOM under different motion states are 55-60 μV.

Fabrication and characterization of ultra-thin ZnO based bottom gate thin film transistor for UV detection

An RF sputtered ZnO thin film was utilized in a thin film transistor (TFT) fabrication. The film was fabricated on SiO2 gate oxide that was thermally grown on Si Substrate. Few lithography steps were used to fabricate the device and device structure was proved to be a bottom gate TFT. The grown film was ultra thin of 25 nm thickness and the Si wafer was n-type. The structural and optical properties of ZnO films were investigated by Field Emission Scanning Electron Microscopy (FESEM), X-Ray Diffraction (XRD) and Photo luminance (PL) spectroscopy. The photo luminance study confirmed a high-quality absorbance in UV spectra and relatively good transmittance in the visible region. The electrical performance of the transistor was studied using Proxima B1500 and the on/off current ratio was measured to be ∼107. The ZnO bottom gate TFT is simulated using the commercial TCAD tool Silvaco ATLAS™. Later the simulated I–V characteristic of the device is compared with the experimental one and both are in fairly good agreement. Further the UV detection capability of the fabricated device was studied by using UV LED light of 365 nm wavelength. The measured value of threshold voltage was found to be 9V under dark light and 10V under UV light.

Improved electro-optical and dielectric properties of polymer dispersed liquid crystal doped with disperse dye red 1 and carbon nanoparticles

ABSTRACT Disperse dye red 1 (DR1) and carbon nanoparticles (CNPs) were doped separately to form polymer dispersed liquid crystal films, namely, DPDLC & CPDLC. Nematic liquid crystal (LC) and photopolymer NOA-65 were used to prepare these composite films using polymerisation-induced phase separation (PIPS) technique. In this research work, it is demonstrated that the minute concentration (0.05% wt./wt.) of DR1 and CNPs controls the LC droplet alignment and LC droplet size in polymer dispersed liquid crystal (PDLC) film. The effect of DR1 and CNPs on PDLC film has been investigated in terms of LC droplet size, transition temperature, voltage-transmittance characteristic, contrast ratio, response time, haze, and dielectric measurements. The obtained results reveal that the threshold voltage values of the composite film get reduced from 34.87 V (undoped) to 10.19 and 9.26 V, for 0.05% of DR1 and CNPs doping, respectively. The DR1 (0.05%) doped film shows improved contrast of the undoped film as compared to CNPs (0.05%) film, whereas CNPs (0.05%) doped film shows a faster response time of 2.81 ms as compared to DR1 (0.05%) doped film (3.14 ms). Dielectric analysis of undoped, DPDLC, and CPDLC films represents Debye type relaxation mode.

Dual-channel P-type ternary DNTT–graphene barristor

P-type ternary switch devices are crucial elements for the practical implementation of complementary ternary circuits. This report demonstrates a p-type ternary device showing three distinct electrical output states with controllable threshold voltage values using a dual-channel dinaphtho[2,3-b:2′,3′-f]thieno[3,2-b]-thiophene–graphene barristor structure. To obtain transfer characteristics with distinctively separated ternary states, novel structures called contact-resistive and contact-doping layers were developed. The feasibility of a complementary standard ternary inverter design around 1 V was demonstrated using the experimentally calibrated ternary device model.

A Threshold Voltage Model for AOS TFTs Considering a Wide Range of Tail-State Density and Degeneration

There have been significant differences in principle electrical parameters between amorphous oxide semiconductor (AOS) thin-film transistors (TFTs) and silicon-based devices for their distinct conduction mechanisms. Additionally, threshold voltage is one of the key parameters in device characterization and modeling. In this work, a threshold voltage model is developed for AOS TFTs considering the various density of exponential tail states below the conduction band, including degenerate conduction. The threshold condition is defined where the density ratio of free carriers to the trapped carriers reaches a critical value depending on the distribution parameters of tail states. The resulting threshold voltage expression is fully analytical and is of clear physical meaning, with simple parameter extraction methods. Numerical and experimental verifications show that this model provides appropriate values of threshold voltage for devices with different sub-gap tail states, which could be a useful method for identifying the threshold voltage of a large variety of AOS TFTs.

Investigation of the Efficiency of Shielding Gamma and Electron Radiation Using Glasses Based on TeO2-WO3-Bi2O3-MoO3-SiO to Protect Electronic Circuits from the Negative Effects of Ionizing Radiation.

This article considers the effect of MoO3 and SiO additives in telluride glasses on the shielding characteristics and protection of electronic microcircuits operating under conditions of increased radiation background or cosmic radiation. MoO3 and SiO dopants were chosen because their properties, including their insulating characteristics, make it possible to avoid breakdown processes caused by radiation damage. The relevance of the study consists in the proposed method of using protective glasses to protect the most important components of electronic circuits from the negative effects of ionizing radiation, which can cause failures or lead to destabilization of the electronics. Evaluation of the shielding efficiency of gamma and electron radiation was carried out using a standard method for determining the change in the threshold voltage (∆U) value of microcircuits placed behind the shield and subjected to irradiation with various doses. It was established that an increase in the content of MoO3 and SiO in the glass structure led to an increase of up to 90% in the gamma radiation shielding efficiency, while maintaining the stability of microcircuit performance under prolonged exposure to ionizing radiation. The results obtained allow us to conclude that the use of protective glasses based on TeO2–WO3–Bi2O3–MoO3–SiO is highly promising for creating local protection for the main components of microcircuits and semiconductor devices operating under conditions of increased background radiation or cosmic radiation.

Effect of the gate electrodes/water interface on the performance of ZnO-based water gate field-effect transistors

Field-effect transistors can be gated with water as the dielectric due to the formation of electrical double layers at water interfaces, which results in high specific capacitance and low voltage operation. The incorporation of analytes in aqueous suspension influences the water's electrical properties changing the water-gated field-effect transistors (WGFETs) performance and allowing it to be used as sensor and biosensor platforms. However, the material used as a gate electrode can affect the transistor's performance due to several factors, as the metal work function, its electrochemical range, and the presence of physicochemical reactions. Here, we evaluated the performance of WGFETs using spray-deposited zinc oxide (ZnO) as the active layer and five different gate electrodes: graphite pencil (GP), gold (Au), indium tin oxide (ITO), tungsten (W), and tin (Sn). The threshold voltage (VTH) values found were 0.41, 0.44, 1.12, 1.21 and 1.74 V for the Sn, W, Au, GP and ITO electrodes, respectively. The field-effect mobility was strongly influenced by the gate material, varying in the range from 0.07 to 0.46 cm2/Vs. The WGFETs operating with W and Sn gates showed the highest Ion/Ioff ratio and the lowest VTH when compared to the other electrodes. However, this characteristic may be associated with the formation of a natural oxide layer at its interface with water, which could be undesirable from the stability view. The use of ITO as the gate electrode resulted in a large hysteresis and two orders of magnitude smaller current in the output curve compared to Au and GP. Among the materials used as the gate electrode, GP stands out mainly because it gives the lowest subthreshold swing (SS = 90 mV/dec) and the highest transconductance (gm = 0.40 mS). Also, the GP matches with ZnO as biocompatible material for low-cost, eco-friendly, and metal-free electronics. In summary, the results showed that the gate electrode significantly influences the main parameters of the device and, therefore, should be an analysis factor when aiming to use WGFETs as sensors.

Analysis of electrical characteristics and electroluminescent efficiency of field induced contact-DGOLET1

This research paper discusses the significance development in field-induced contact dual-gate organic light emitting transistor (FIC-DGOLET) device architecture and characteristics. The device behaviour is analyzed and observed significant value of electroluminescent efficiency. The deep investigation of FIC-DGOLET device is discussed in this paper, where impact of varying the various parameters such as thickness of organic semiconductor (OSC) materials from the range of 400 nm to 200 nm at altered value of threshold voltage by using 2D ATLAS simulator. Its theoretical calculation influence over the dynamic control of the device characteristics such as saturated drain current (Ids), mobility (μ), threshold voltage (Vth) as well as sub threshold swing. The FIC-DGOLET is a dual-gate transistor which also emits light by the operations of two accumulated regions, that are electrons and holes which is not completely overlapped to each other. The leakage current in DG-OLET can be reduced to the extent that 70% than single gate OLET (SG-OLET). The recombination zone mechanism of FIC-DGOLET plays a vital role in its performance, where we get comparable value of electroluminescent efficiency with reported, low value of exciton quenching and current densities. The extracted parameters of DG-OLETs are like drive current of 100A, Ion/off 108, threshold voltage Vth of 1.3 V at Vgs of –3 V and Vds of 0 to –3 V. These extracted performance parameters are very helpful in designing of flexible display applications.

Design and Analysis of Secure Quasi-Adiabatic Tristate Physical Unclonable Function

Hardware security modules have become quintessential as the digital systems continue evolving. Physical Unclonable Function (PUF) is a hardware security module that exploits the intrinsic variations in manufacturability of integrated circuits. Proposed Quasi-adiabatic Tristate PUF is a weak PUF which makes use of the inherent mismatches found in the threshold voltage values of PMOS transistors, which inadvertently is introduced due to manufacturing process variations of ICs. The proposed design demonstrates lower energy consumption than those configured using comparable quasi-adiabatic logic counterparts, under varying temperature and peak voltage conditions. The design is compared using SRAM PUF design based on adiabatic logic and it is shown that the proposed one is having better uniqueness and reliability at different environmental conditions. The proposed PUF can generate 128 CRPs which can be well suited for IoT and RFID applications that require less energy to operate.