Abstract
Moore’s law states that the technical innovations are being absorbed already. The device’s controllability has dramatically improved since moving from a straightforward MOSFET constructed with a single control gate to one with many control gates. In this research paper, the device-level simulation of vertically stacked GAA nanosheet FET is performed, for which the various geometrical variations are calibrated. This research paper examines the impact of these geometrical variations on the device’s performance. The most prominent parameters like I ON, I OFF, SS, DIBL, switching ratio, and Threshold voltage values are analyzed. For the device to be considered to have better performance I ON should be maximum, I OFF should be minimum. Hence to obtain this the thickness of the nanosheet is varied on the scale of 5 nm to 9 nm, and the width is varied from 10 nm to 50 nm. The device simulation and analysis are performed using the Visual TCAD−3D Cogenda tool.
Published Version
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