UWB LNA Research Articles

A UWB LNA with cascade of CCG and CS stage with improvement in gain and noise in 90-nm technology

A UWB LNA with cascade of CCG and CS stage with improvement in gain and noise in 90-nm technology

A high linearity UWB LNA using a novel linearizer feedback, based on complementary derivation superposition techniques

A high linearity UWB LNA using a novel linearizer feedback, based on complementary derivation superposition techniques

Noise suppression in a common-gate UWB LNA with an inductor resonating at the source node

In this paper, a noise suppression circuit is proposed and investigated by using resonance technique at the source. Resonance in the source node of the common-gate structure blocks the noise path while transferring the signal from input to output. Through proper analysis, a common gate structure with an active load is improved. As a result, a complementary common gate structure is introduced. A complementary common-gate structure with resonance in the source node can overcome the trade-off between noise and gain in the first stage. Hence, this structure is optimum in terms of the trade-off between gain and noise as well as power dissipation and linearity. Finally, a very-low-noise amplifier is implemented by this method and the post-layout simulation results are obtained: average power gain: 15.8 dB, minimum noise figure: 1.7 dB, bandwidth: 3.1–4.8 GHz, power dissipation of two stage: 11.28 mW, 1-dB compression point at input power: −4.67 dBm, and IP3 at input power: 8.32 dBm.

A 0.9 V, 4.57 mW UWB LNA with Improved Gain and Low Power Consumption for 3.1–10.6 GHz Ultra-Wide Band Applications

In this paper, we present a 0.9 V, 4.57 mW UWB LNA with improved gain and low power consumption for 3.1–10.6 GHz ultra-wide band applications. In its input stage, a common gate amplifier is used to achieve approximately $$50\,\Omega$$ input resistance across the entire band, instead of using a common source stage. However, the current reused technique is used to save power consumption by using the same DC current path for both transistors in the designed circuit instead of utilizing two stage cascade configuration. The output matching is achieved by tuning the total parasitic capacitance with the inductor $$\hbox {L}_{d1}$$ at the output node. In its inter stage, inter stage matching technique is used to make the flat gain response and to extend the bandwidth, simultaneously. From simulation results, the designed LNA shows an average power gain $$\hbox {S}_{21}$$ of 15.8 dB with the gain variation of $$\pm 0.97 \hbox { dB}$$ , an input return loss $$\hbox {S}_{11}$$ of −30 to −10 dB, a high reverse isolation $$\hbox {S}_{12}$$ of −59 to −43 dB, output return loss $$\hbox {S}_{22}$$ of −16 to −10 dB, and a small group-delay variation of $$\pm 34$$ ps across the entire band. It also shows minimum achievable noise figure below 3.2 dB, and a power consumption of 4.57 mW from a supply voltage of 0.9 V. When a two tone test is performed at 8 GHz with 10 MHz spacing, the linearity of the designed LNA such as 1-dB compression point and third order input intercept point are −22.5 and −9 dBm, respectively.

A CMOS 3–12-GHz Ultrawideband Low Noise Amplifier by Dual-Resonance Network

A low-power and high power-gain ( $S_{21}$ ) ultrawideband low noise amplifier (UWB LNA) with flat noise figure (NF) based on Global Foundies 0.13- $\mu \text{m}$ CMOS technology is reported. The load effect of common-gate (CG) topology is applied with dual-resonance load network for both wideband input matching and NF flatness. Combined with inductive-series peaking technique, the frequency response of CG-common-source cascade topology is further extended. The LNA circuit achieves the high and flat power gain of 13.5 ± 1.5 dB with input return loss better than 13 dB and a flat NF of 4.3 dB ±0.4 dB for frequencies 3–12 GHz. The fabricated LNA occupies a die area of 1.09 0.8 mm2 including pads and draw 8.5 mW from 1.2-V dc supply.

A linear, low power, 2.5-dB NF LNA for UWB application in a 0.18 μm CMOS

This paper presents an ultra-wideband common-gate low-noise amplifier (UWB CG-LNA) that employs negative feedback to overcome the trade-off that exists between noise and input impedance matching while preserving linearity, stability, and low power operation. The proposed LNA has been designed and simulated via TSMC 0.18-μm CMOS. UWB LNA operates from 3.1 to 10.1GHz. Designed LNA consumes 2.3mA from a 1.8-V supply. Post-layout simulation shows that LNA achieves a maximum voltage gain of 13.7dB, a minimum noise figure of 2.5dB, better than −10dBS11 and +4.5 to +9.5dBm IIP3 across the entire bandwidth. The Volterra series has been used to analyze the linearity of circuit.

Systematic Approaches of UWB Low-Power CMOS LNA with Body Biased Technique

This paper presents research on a low power CMOS UWB LNA based on a cascoded common source and current-reused topology. A systematic approach for the design procedure from narrow band to UWB is developed and discussed in detail. The power reduction can be achieved by using body biased technique and current-reused topology. The optimum width of the major transistor device M1 is determined by the power-constraint noise optimization with inner parasitic capacitance between the gate and source terminal. The derivation of the signal amplification S21 by high frequency small signal model is displayed in the paper. The optimum design of the complete circuit was studied in a step by step analysis. The measurements results show that the proposed circuit has superior S11, gain, noise figure, and power consumption. From the measured results, S11 is lower than -12 dB, S22 is lower than -10 dB and forward gain S21 has an average value with 12 dB. The noise figure is from 4 to 5.7 dB within the whole band. The total power consumption of the proposed circuit including the output buffer is 4.6 mW with a supply voltage of 1 V. This work is implemented in a standard TSMC 0.18 μm CMOS process technology.

Analysis and design of a compact ultrawideband LNA with 2.3 ± 0.1 dB NF and ±14.6 ps group‐delay‐variation in 0.18‐µm CMOS

ABSTRACTA low‐noise figure (NF) and high power gain (S21) 3–10 GHz ultrawideband low‐noise amplifier (UWB LNA) with excellent phase linearity using standard 0.18‐µm CMOS technology is reported. An enhanced π‐match input network is used to achieve wideband input impedance matching. Both high and flat S21 and low and flat NF frequency responses are achieved by tuning the pole frequencies and pole quality factors of the second‐order gain and NF frequency responses to approximate the maximally flat condition simultaneously. The LNA consumes 18 mW, achieving S11 better than −10 dB for frequency lower than 12.2 GHz and group‐delay‐variation smaller than ±14.6 ps for frequencies 3–10 GHz. Additionally, high and flat S21 of 13.7 ± 1.5 dB is achieved for frequencies 1–12.5 GHz, which means the corresponding 3‐dB bandwidth is 11.5 GHz. Furthermore, the LNA achieves minimum NF of 2.2 dB at 4 GHz and NF of 2.3 ± 0.1 dB for frequencies 3–10 GHz, one of the best NF results ever reported for a 3–10 GHz CMOS UWB LNA. The measured input third‐order intermodulation point (IIP3) is −0.2 dBm at 6 GHz. The chip area is only 0.601 × 0.662 mm2 (i.e., 0.4 mm2) excluding the test pads. © 2014 Wiley Periodicals, Inc. Microwave Opt Technol Lett 56:2047–2053, 2014

A SiGe LC-ladder low noise amplifier with base resistance match, gain and noise flatness for UWB applications

This study presents a 3.1–10.6GHz ultra-wideband low noise amplifier (UWB LNA) in 0.18µm SiGe HBT technology. To achieve a good input match, parasitic base resistance in a bipolar transistor and an LC-ladder filter are included into calculations with the common-emitter topology using shunt–shunt capacitive feedback. Both high and flat power gain (S21) and low and flat noise figure (NF) are achieved by adjusting the pole and zero in amplifying stage and quality factors of the fourth-order input network. Design equations for performances such as gain, noise figure and linearity IIP3 are derived especially on gain flatness and noise flatness. LNA dissipates 33mW power and achieves S21 of 20.65+0.7dB, NF of 2.79+0.2dB over the band of 3.1–10.6GHz. The simulated input third-order intermodulation point (IIP3) is −17dBm at 10GHz.

High-Performance Wideband Low-Noise Amplifier Using Enhanced $\pi$-Match Input Network

A low noise-figure (NF) and high power gain (S21) 3 ~ 10 GHz ultra-wideband low-noise amplifier (UWB LNA) with excellent phase linearity using 0.18 μm CMOS technology is reported. An enhanced π-match input network is used to achieve wideband input impedance matching as well as high and flat S21. To achieve low and flat NF, the pole frequency and pole quality factor of the second-order NF frequency response are tuned to approximate the maximally flat condition. The LNA consumes 18 mW, achieving S11 better than -10 dB for frequency lower than 12.2 GHz and group-delay (GD) variation smaller than ±14.6 ps for frequencies 3 ~ 10 GHz. Additionally, high and flat S21 of 13.7 ± 1.5 dB is achieved for frequencies 1 ~ 12.5 GHz, which means the corresponding 3-dB bandwidth is 11.5 GHz. Furthermore, the LNA achieves minimum NF of 2.2 dB at 4 GHz and NF of 2.3 ± 0.1 dB for frequencies of 3 ~ 10 GHz, one of the best NF results ever reported for a 3 ~ 10 GHz CMOS LNA.

A Low Voltage Full-band Folded Cascoded UWB LNA with Feedback Topology

A Low Voltage Full-band Folded Cascoded UWB LNA with Feedback Topology

Design of low power UWB LNA based on common source topology with current-reused technique

This paper presents two low power UWB LNAs with common source topology. The power reduction is achieved by the current-reused technique. The gain and noise enhancement of the proposed circuit is based on an output buffer which is used by a common source amplifier with shunt–shunt feedback. Chip1 is an adopted T-match input network of 50Ω matching in the required band. Measurements show that the S11 and S22 are less than −10dB, and the maximum amplifier gain S21 gives 9.7dB, and the noise figure is 4.2dB, the IIP3 is −8.5dBm, and the power consumption is 11mW from 1.1V supply voltage. The input matching of chip2 is adopted from a LC high pass filter and source degenerated inductor. The output buffer with the RC-feedback topology can improve the gain, increase the IIP3, restrain the noise, improve the noise figure and decrease the DC power dissipation. Measurements show 13.2dB of power gain, 3.33dB of noise figure, and the IIP3 is −3.3dBm. It consumes 9.3mW from 1.5V supply voltage. These two chips are implemented in a 0.18μm TSMC CMOS process.

A 3.1–10.6‐GHz Current‐Reused CMOS Ultra‐Wideband Low‐Noise Amplifier Using Self‐Forward Body Bias and Forward Combining Techniques

ABSTRACTA 3.1–10.6‐GHz ultra‐wideband low‐noise amplifier (UWB LNA) with excellent phase linearity property (group‐delay variation is only ±19.46 ps across the whole band) using standard 0.18‐µm CMOS technology is reported. Current reused, self‐forward body bias and forward combining techniques are used to achieve low power and high‐power gain (S21). Both high and flat S21 and low and flat noise figure (NF) frequency responses are achieved by tuning the pole frequencies and pole quality factors of the second‐order gain and NF frequency responses to approximate the maximally flat condition simultaneously. The LNA dissipates 6.93‐mW power and achieves NF of 3.76 at 10 GHz. In addition, the LNA achieves input return loss (S11) smaller than −10.6 dB, and high and flat S21 of 11.02 ± 0.47 dB over the 3.1–10.6‐GHz band. The corresponding figure of merit (FOM) is 3.11 GHz/mW, one of the lowest FOMs ever reported for a 3.1–10.6 GHz CMOS UWB LNA. The measured input third‐order intermodulation point (IIP3) is −3.6 dBm at 6 GHz. © 2013 Wiley Periodicals, Inc. Microwave Opt Technol Lett 55:2296–2302, 2013

Interference Rejection in UWB LNA using Front-End Triode MOSFET

In this study, an Ultra Wide Band Low Noise Amplifier (UWB LNA) with new input stage for interference rejection is presented. In this scheme, a common gate front end MOS device in triode mode is used to reject in-band and out-band interferences. Furthermore, advantage of weak inversion mode of MOS device is used. While this stage has no DC power consumption, it is possible to easily reject in band and out band interferences with 12.5 and 9.2 dB, respectively. In order to increase power gain of the circuit two stages are added as an amplifier to the circuit. Also, in order to improve the Noise Figure (NF) and bandwidth of the circuit, the advantages of thermal noise cancellation technique in the second stage and the series-peaking method in the output buffer are used. The circuit is design in 0.18 μm technology. Simulation results show peak gain of 17.6 dB in the low band (3.1-4.75 GHz) and 15.6 dB in the high band (6.1-10.6 GHz). Minimum NF in mentioned frequency band is 3 and 2.3 dB, respectively. Hence, this circuit rejects in band and out band interferences 15.6 and 11.5 dB, respectively, while UWB LNA consumes 16 mW DC power from 1.8 V. The s11 is less than -9.6 dB over entire bandwidth since worst value of IIP3 over entire bandwidth is -14 dBm which occurs at 10.6 GHz.

CMOS Ultra-Wideband Low Noise Amplifier Design

This paper presents the design of ultra-wideband low noise amplifier (UWB LNA). The proposed UWB LNA whose bandwidth extends from 2.5 GHz to 16 GHz is designed using a symmetric 3D RF integrated inductor. This UWB LNA has a gain of 11 ± 1.0 dB and a NF less than 3.3 dB. Good input and output impedance matching and good isolation are achieved over the operating frequency band. The proposed UWB LNA is driven from a 1.8 V supply. The UWB LNA is designed and simulated in standard TSMC 0.18 µm CMOS technology process.

A novel configuration for UWB LNA suitable for low-power and low-voltage applications

Two UWB LNAs based on a new configuration suitable for low-power and low-voltage applications are presented. The proposed configuration saves bias circuit because of sharing only a bias circuit. In designing LNA-1 good phase linearity property achievement is followed for low-power and low-voltage applications, while in LNA-2 the main concerns are high power gain, by keeping low-power consumption, and small chip area. By taking advantages of resistive-feedback and RLC load, wideband input matching is obtained. Based on the proposed configuration, accompany with complete noise analysis, noise of LNA-2 is highly suppressed and flat noise figure is reaped. The 130nm CMOS LNA-1 and LNA-2 dissipate 2.95mW and 6.09mW, respectively, from 0.7V supply voltage, without using of forward-body-bias technology. Input return loss of both LNAs is below than −10.5dB while LNA-1 achieves average power gain of 9dB and LNA-2 17dB. The group-delay variation of LNA-1 is about ±6.1ps over the band of 3.1–10.6GHz. The NF of LNA-2 is 2.4–2.89dB over the whole band of interest.

11.81 mW 3.1–10.6 GHz ultra‐wideband low‐noise amplifier with 2.87 ± 0.19 dB noise figure and 12.52 ± 0.81 dB gain using 0.18 μm CMOS technology

AbstractA 3.1–10.6 GHz ultra‐wideband low‐noise amplifier (UWB LNA) with excellent phase linearity property (group‐delay variation is only ±15.79 ps across the whole band) using standard 0.18 μm CMOS technology is reported.Both high and flat power gain (S21) and low and flat noise figure (NF) frequency responses are achieved by tuning the pole frequencies and pole quality factors of the second‐order gain and NF frequency responses to approximate the maximally flat condition simultaneously. The LNA dissipates 11.81 mW power and achieves input return loss (S11) smaller than −10.25 dB, high and flat S21 of 12.52 ± 0.81 dB, and low and flat NF of 2.87 ± 0.19 dB over the 3.1–10.6 GHz band. To the author's knowledge, this is one of the lowest NFs ever reported for a 3.1–10.6 GHz CMOS UWB LNA. The measured 1‐dB compression point and input third‐order intermodulation point are −16 and −6.2 dBm, respectively, at 6 GHz. © 2012 Wiley Periodicals, Inc. Microwave Opt Technol Lett 54:1445–1450, 2012; View this article online at wileyonlinelibrary.com. DOI 10.1002/mop.26813

A 3.1‐dB NF, 21.31 dB gain micromachined 3–10 GHz distributed amplifier for UWB systems in 0.18‐μm CMOS technology

AbstractA high‐gain and low‐noise micromachined CMOS distributed amplifier (DA) using cascaded gain cell, which constitutes an inductively parallel‐peaking cascode‐stage with a low‐Q RLC load and an inductively series‐peaking common‐source stage, is demonstrated.Flat and high S21 and flat and low noise figure (NF) are achieved simultaneously by adopting a slightly under‐damped Q‐factor for the second‐order transconductance frequency response of the proposed cascaded gain cell. The two‐stage DA consumes 37.8 mW and achieves flat and high S21 of 20.47 ± 0.72 dB with an average NF of only 3.3 dB over the 3∼10 GHz band of interest, one of the best reported NF performances for a CMOS UWB DA or LNA in the literature. In addition, the result shows that a 0.84‐dB increase in average S21 (from 20.47 to 21.31 dB) and a 0.2‐dB decrease (from 3.3 to 3.1 dB) in average NF are achieved mainly due to the improvement of the quality factor of the inductors in the DA. This means that this DA architecture in conjunction with the backside ICP dry‐etching technique is very promising for high‐performance 3∼10 GHz UWB communication systems. © 2012 Wiley Periodicals, Inc. Microwave Opt Technol Lett 54:1163–1167, 2012

A Low Voltage High Gain Transformer Noise-Canceling Current Mode Ultrawideband CMOS Low Noise Amplifier

This paper presents a novel current mode differential UWB LNA. A common-gate stage with transformer realizes a low noise input matching and produces a current gain. The output of the LNA is differential current, which can avoid the current-to-voltage conversion. The LNA is simulated with TSMC 0.18 μm RF CMOS process. Simulation results show that the max noise figure is only 2.65 dB, transconductance gain is larger than 18.7 dB, input reflection coefficient is lower than -9.9 dB, and third order input intercept point is about 2.8 dBm over 3–5 GHz. With a voltage of 0.8 V, the power consumption is 11 mW. A comparison with conventional UWB LNA shows that this LNA has advantages of low voltage, low noise, high gain, and high linearity.

3.2–9.7 GHz ultra-wideband low-noise amplifier with excellent stop-band rejection

A low-power 3.2–9.7 GHz ultra-wideband low-noise amplifier (UWB LNA) with excellent stop-band rejection by 0.18 µm CMOS technology is demonstrated. High stop-band rejection is achieved by using a passive bandpass filter (BP-filter) with three finite transmission zeros (in the input terminal), one of which (ωz1=0.9 GHz) is in the low-frequency stop-band and the other two (ωz3 and ωz5) are in the high-frequency stop-band. In addition, an active notch filter is used in the output terminal to introduce another low-frequency stop-band transmission zero (ωz2) at 2.4 GHz. The LNA consumes 4.68 mW and achieves S11 of −10 to −39.5 dB, S21 of 9.3±1.5 dB, and an average NF of 6 dB over the 3.2–9.7 GHz band. The measured stop-band rejection is better than 21.6 dB for frequencies DC–2.5 and 11.2–20 GHz.