Use Of VHDL Research Articles

FPGA Implementation of Vending Machine

This paper aims to create a coin processing system-based vending machine that can handle input coin values and dispense or return change as required, utilizing a single-state machine designed with the Mealy state machine model. To implement this design VHDL is used, which is a hardware description language capable of producing efficient and reliable system development. Xilinx VIVADO 2017.4 software tool is used to simulate and test the system, allowing for efficient debugging of FPGA designs. The system is deployed on a Nexys 4 DDR FPGA Board development board, enabling practical and robust implementation. This particular design offers great versatility, making it suitable for a wide range of applications, such as vending machines, parking meters, and other automated systems that require coin processing. The Mealy state machine model proves to be an efficient and reliable approach to coin processing, and the use of VHDL and FPGA board ensures a practical and effective implementation of the design.

On-chip debugging for microprocessor design

This article proposes a closer-to-metal approach of RTL inspection in microprocessor design for use in education, engineering, and research. Signals of interest are tapped throughout the microprocessor hierarchical design and are then output to the top-level entity and finally displayed to a VGA monitor. Input clock signal can be fed as slow as one wish to trace or debug the microprocessor being designed. An FPGA development board, along with its accompanying software package, is used as the design and test platform. The use of VHDL commands ’type’ and ’record’ in the hierarchy provides key ingredients in the overall design, since this allows simple, clean, and tractable code. The method is tested on MIPS single-cycle microprocessor blueprint. The result shows that the technique produces more consistent display of the true contents of registers, ALU input/output signals, and other wires – compared to the standard, widely-used simulation method. This approach is expected to increase confidence in students and designers since the reported signals’ values are the true values. Its use is not limited to the development of microprocessors; every FPGAbased digital design can benefit from it.

Design and FPGA Implementation of LDPC Decoder Chip for Communication System using VHDL

The paper emphasized on the design and application of LDPC coding system using FPGA. The LDPC decoder is used to decode the information/data received from the channel after correcting channel errors based on parity bits selection of the data bits. In the communication system, when a parity check failure is noticed, the information from the multiple parity bits can be used to recover the original data bit. The LDPC decoder implementation is done using Shift-Register based design to reduce the complexity. The Modified Sum Product (MSP) method is used to decode, the signal. The system performance is also analyzed with hardware chip and timing parameters with FPGA implementation of the same system. The chip design of the LDPC chip is done usingVivado 17.4, programmed with the use of VHDL and hardware performance is estimated on Virtex-5 FPGA.

Efficient Hardware Implementation of the Pipelined DES Encryption Algorithm Using FPGA

This paper presents a high throughput reconfigurable hardware implementation of DES Encryption algorithm.This achieved by using a new proposed implementation of the DES algorithm using superpipelinedconcept.DES are simulated using Xilinx 9.2i software with the use of VHDL as the hardware description languageand implemented using Spartan-3E FPGA kit.The DES Encryption algorithm achieved a high throughput of18.327Gbps and 3235 number of Configurable Logic Blocks (CLBs), obtaining the fastest hardware implementation with better area utilization.Comparison is made between the proposed implementation and other recent implementations. The comparison results indicate that a high throughput with optimized resource utilization scan be achieved using a super pipelined concept on the proposed design in a single FPGA chip.

Research of Fuzzy PID Control Based on VHDL

This paper describes the use of VHDL and fuzzy controller design process.Compared with conventional PID control, fuzzy control is not dependent on the accurate mathematical model of the controlled object. The implementation of integrated practical operating experience and the operation is simple, fast response, anti-interference ability, strong robustness parameters of controlled object. In response to the limitations of the traditional PID control algorithm in the control field, the fuzzy control theory with the traditional PID control algorithm by combining the parameters self-tuning function, the proposed fuzzy self-tuning PID controller design method and algorithm-depth study analysis.

SoC with an integrated DSP and a 2.4-GHz RF transmitter

We present a system-on-chip (SoC) that integrates a TMS320C54x digital signal processor (DSP), which is commonly used in cellular phones, with a multigigahertz digital RF transmitter that meets the Bluetooth specifications. The RF transmitter is tightly coupled with the DSP and is directly mapped to its address space. The transmitter architecture is based on an all-digital phase-locked loop (ADPLL), which is built from the ground up using digital techniques and digital creation flow that exploit high speed and high density of a deep-submicrometer CMOS process while avoiding its weaker handling of voltage. The frequency synthesizer features a wideband frequency modulation capability. As part of the digital flow, the digitally controlled oscillator (DCO) and a class-E power-amplifier are created as ASIC cells with digital I/Os. All digital blocks, including the 2.4-GHz logic, are synthesized from VHDL and auto routed. The use of VHDL allows for a tight and seamless integration of RF with the DSP. To take advantage of the direct DSP-RF coupling and to demonstrate a software-defined radio (SDR) capability, a DSP program is written to perform modulation of the GSM standard. The chip is fabricated in a baseline 130-nm CMOS process with no analog extensions and features high logic gate density of 150 kgates per mm/sup 2/. The RF transmitter area occupies only 0.54 mm/sup 2/, and the current consumption (including the companion DSP) is 49 mA at 1.5-V supply and 4 mW of RF output. This proves attractiveness and competitiveness of the "digital RF" approach, whose goal is to replace RF functions with high-speed digital logic gates.

Efficient isolation, purification, and characterization of the Helicoverpa zea VHDL receptor

The study of fat body receptors (e.g., VHDL receptor) in Lepidoptera has been irksome due to the fact that isolation and purification of these proteins are difficult and resulted in extremely low yields. A rapid and efficient method is presented for the purification of Helicoverpa zea VHDL receptor by the use of VHDL–biotin ligand complexed to streptavidin coated magnetic beads. The technique can be easily applied to other ligands and allows for the purification of membrane proteins with higher yields compared to previously used methods involving immunopurification. Although the purified protein can be characterized by Western and non-radioactive ligand blots using enhanced chemiluminescence (ECL), a non-radioactive ligand blot method using VHDL–FITC is presented, which allows for the quick analysis of the receptor directly from the blot under standard UV light. Sufficient receptor protein has been derived for amino acid analysis, receptor-ligand and xenobiotic binding studies.

Digital system simulation with VHDL in a high-level synthesis system

This paper presents the use of VHDL to simulate the intermediate design representation in a high-level synthesis system. The design representation is captured by an extended time Petri net notation and is used throughout the synthesis process. We have developed an algorithm to convert the design representation into a VHDL description. As a result, digital system designs can be simulated together with the behavioral models of the primitive register-transfer level components which are also described in VHDL. The main feature of our approach is that the intermediate results (as well as the final results) of the high-level synthesis process can be simulated at any time and the simulation results can be used to guide the synthesis process.