Use Of Routing Tables Research Articles

METHOD OF THE SENSOR NETWORK RESOURCES ALLOCATION IN THECONDITIONS OF EDGE COMPUTING

The article describes the developed methodology, which allows to reduce the resource usage of the wireless sensor network by reducing the cost of sending data using a special routing table. The simulator was developed that allows you to explore and compare the use of routing table and random routing. The analysis of the data showed the advantages of using the established methodology, which can be applied to any networks that use edge computing and have intelligent data processing.

Characterizing the Analogy Between Hyperbolic Embedding and Community Structure of Complex Networks.

We show that the community structure of a network can be used as a coarse version of its embedding in a hidden space with hyperbolic geometry. The finding emerges from a systematic analysis of several real-world and synthetic networks. We take advantage of the analogy for reinterpreting results originally obtained through network hyperbolic embedding in terms of community structure only. First, we show that the robustness of a multiplex network can be controlled by tuning the correlation between the community structures across different layers. Second, we deploy an efficient greedy protocol for network navigability that makes use of routing tables based on community structure.

Application-aware Multi-Objective Routing based on Genetic Algorithm for 2D Network-on-Chip

This paper presents a technique using a genetic algorithm to compute an efficient routing for an application-specific NoC (Network-on-Chip). The main goal of this paper is to introduce multi-objective optimization techniques to address the NoC routing. Thus, Pareto optimization has been used to determine non-dominated solutions according to two fixed objectives: (i) avoiding the reuse of same links as far as possible to reduce congestion; (ii) reducing the number of loops to limit the risk of deadlocks. The proposed method called MORGA (Multi-Objective Routing based on Genetic Algorithm) uses two steps: (i) an off-line process consisting at selecting a non-dominated solution among a pre-calculated population of solutions; (ii) an on-line process allowing the data transmission based on the built solution by the use of routing tables. MORGA is also applicable in the presence of permanent faulty links by calculating fault-free solutions. A reconfiguration of routing tables is performed when a new application is loaded on the system. Results show how a selection of the most appropriate solution can provide considerable improvement in performance.

Hybrid fault tolerant routing algorithm in NoC

Network-on-Chip has been a growing design paradigm with the rise in Multi-Processor System on Chip (MPSoCs) primarily due to its scalability. While regular meshes (2 or 3-dimensional) are the usual proposal for such a paradigm, a real chip may not follow it. Heterogeneous cores, hardware failures or manufacturing defects can possibly cause irregular topologies in a Network-on-Chip. Selection of a routing algorithm is an important challenge in NoC design as it affects power consumption, communication latency and overall system performance. Routing can be supported in such faulty environment by use of routing tables. But this is not a scalable solution as table size grows with network size. Logic Based Distributed Routing (LBDR) is proposed as a new routing implementation technique which offers compact routing implementation and fault tolerance without use of routing table. In this paper we propose a Hybrid Fault Tolerant Routing Algorithm (HFTRA), which aims to provide fault tolerance support in presence of on-chip link failures. Proposed routing is implemented with LBDR scheme. Analysis of the method has shown the effectiveness of proposed scheme as compared to routing tables when implemented using LBDR.

Efficient implementation of distributed routing algorithms for NoCs

Chip multiprocessors (CMPs) are gaining momentum in the high-performance computing domain. Networks-on-chip (NoCs) are key components of CMP architectures, in that they have to deal with the communication scalability challenge while meeting tight power, area and latency constraints. 2D mesh topologies are usually preferred by designers of general purpose NoCs. However, manufacturing faults may break their regularity. Moreover, resource management frameworks may require the segmentation of the network into irregular regions. Under these conditions, efficient routing becomes a challenge. Although the use of routing tables at switches is flexible, it does not scale in terms of latency and area due to its memory requirements. Logic-based distributed routing (LBDR) is proposed as a new routing method that removes the need for routing tables at all. LBDR enables the implementation of many routing algorithms on most of the practical topologies we may find in the near future in a multi-core system. From an initial topology and routing algorithm, a set of three bits per switch/output port is computed. Evaluation results show that, by using a small logic, LBDR mimics the performance of routing algorithms when implemented with routing tables, both in regular and irregular topologies. LBDR implementation in a real NoC switch is also explored, proving its smooth integration in the architecture and its negligible hardware and performance overhead.