Hybrid fault tolerant routing algorithm in NoC

Abstract

Network-on-Chip has been a growing design paradigm with the rise in Multi-Processor System on Chip (MPSoCs) primarily due to its scalability. While regular meshes (2 or 3-dimensional) are the usual proposal for such a paradigm, a real chip may not follow it. Heterogeneous cores, hardware failures or manufacturing defects can possibly cause irregular topologies in a Network-on-Chip. Selection of a routing algorithm is an important challenge in NoC design as it affects power consumption, communication latency and overall system performance. Routing can be supported in such faulty environment by use of routing tables. But this is not a scalable solution as table size grows with network size. Logic Based Distributed Routing (LBDR) is proposed as a new routing implementation technique which offers compact routing implementation and fault tolerance without use of routing table. In this paper we propose a Hybrid Fault Tolerant Routing Algorithm (HFTRA), which aims to provide fault tolerance support in presence of on-chip link failures. Proposed routing is implemented with LBDR scheme. Analysis of the method has shown the effectiveness of proposed scheme as compared to routing tables when implemented using LBDR.