Use Of Memristors Research Articles

VTEAM Model Based In-Memory Computation using Memristors

The recent applications in the computing field deals with huge data processing operations, which involves a lot of data transfer from the memory to processing unit and vice versa. If these data transfers between the CPU and memory are reduced, a lot of time could be saved along with advantage of getting desirable outputs at a lower latency. One of the ways to achieve this is to adopt In-memory computational techniques, where most of the computations happen inside memory itself. Memristive crossbar architecture is a memory architecture which makes use of memristors as memory cells to store data with some added computational capabilities. The need for power efficient computing in the present days motivates the search for new nonvolatile universal memories like memristors. In this paper, we present an optimal way of implementing basic ALU operations in the memristive memory block. A detailed description for simulating this is given, which includes the creation of memristor symbol, choosing a suitable memristive logic to implement basic digital logics, creation of memory crossbar and the way to realize basic ALU operations.

Aspects of the a-TiOx memristor active medium technology

New physical approaches make fast-response non-volatile resistive memory (ReRAM) very attractive for digital, neuromorphic, and other data processing systems considered in many previous publications. Even though the effect of resistance and memory switching in metal-dielectric-metal structures is well known, the physical mechanisms underlying these phenomena are still vague. Considerable instability and insufficient reproducibility of electrical characteristics are the major factors that hold back the practical use of memristors. This problem can be solved by combining the theory of filaments and physics of amorphous wide-bandgap semiconductors which make up the majority of active memristor media currently being investigated. The properties of amorphous and crystalline nanostructures are radically different. Being rather specific, the characteristics of amorphous nanostructures are much dependent on the manufacturing technique. The methods of controlling the amorphous state and its stability are the subject of this paper. The conventional technique of electron-beam induced deposition is used to make the samples. Well-studied TiO2 is taken as a base material for active memristor media. The amorphous state of resultant coats is modified by varying the deposition temperature at an unvaried deposition rate, a residual vacuum-chamber pressure, and coat thicknesses. Sensitive surface plasmon resonance method, spectral technique, and total-external-reflection X-ray diffractometry are the tools to control the stability of the coats. In the experiment, we have observed the long and distinct relaxation of the optical parameters of amorphous layers and the manifestation of the development of an inhomogeneous amorphous layer.

Crossbar-Based Memristive Logic-in-Memory Architecture

The use of memristors and resistive random access memory (ReRAM) technology to perform logic computations, has drawn considerable attention from researchers in recent years. However, the topological aspects of the underlying ReRAM architecture and its organization have received less attention, as the focus has mainly been on device-specific properties for functionally complete logic gates through conditional switching in ReRAM circuits. A careful investigation and optimization of the target geometry is thus highly desirable for the implementation of logic-in-memory architectures. In this paper, we propose a crossbar-based in-memory parallel processing system in which, through the heterogeneity of the resistive cross-point devices, we achieve local information processing in a state-of-the-art ReRAM crossbar architecture with vertical group-accessed transistors as cross-point selector devices. We primarily focus on the array organization, information storage, and processing flow, while proposing a novel geometry for the cross-point selection lines to mitigate current sneak-paths during an arbitrary number of possible parallel logic computations. We prove the proper functioning and potential capabilities of the proposed architecture through SPICE-level circuit simulations of half-adder and sum-of-products logic functions. We compare certain features of the proposed logic-in-memory approach with another work of the literature, and present an analysis of circuit resources, integration density, and logic computation parallelism.

Turing Patterns in Memristive Cellular Nonlinear Networks

The formation of ordered structures, in particular Turing patterns, in complex spatially extended systems has been observed in many different contexts, spanning from natural sciences (chemistry, physics, and biology) to technology (mechanics and electronics). In this paper, it is shown that the use of memristors in a simple cell of a spatially-extended circuit architecture allows us to design systems able to generate Turing patterns. In addition, the memristor parameters play a key role in the selection of the type and characteristics of the emerging pattern, which is also influenced by the initial conditions. The problem of finding the regions of parameters where Turing patterns may emerge in the proposed cellular architecture is solved in an analytic way, and numerical results are shown to illustrate the system behavior with respect to its parameters.

A memristor-based Wien-bridge sinusoidal/chaotic oscillator

This paper presents the experimental results obtained from a memristor-based Wien-bridge oscillator implemented using a new memristor emulator. The memristor emulator can be implemented using off-the-shelf components. The experimental results show that nonlinear chaotic as well as linear oscillations can be obtained from the same circuit by careful adjustment of the value of a single resistor. The proposed circuit can be easily presented in an undergraduate laboratory course to demonstrate the use of memristors in generating chaotic oscillators.

A novel memristive electronic synapse-based Hermite chaotic neural network with application in cryptography

The memristor is a kind of non-linear passive two-terminal electrical device, which is widely applied in neural networks currently. In this paper, a new synaptic weight update learning rule of Hermite neural network is proposed by combining Hermite polynomials with memristors to build a memristive Hermite chaotic neural network (MHCNN). The chaotic series is generated by the weights of the neural network and chaotic initial value. And ultimately we can obtain the ciphertext by encrypting the plaintext. The use of memristors results in a very special neural network, which can not only change the polynomial in neural network but also achieve the diversity, and the confidentiality of communication is also improved effectively.

Resistive switching and synaptic properties of fully atomic layer deposition grown TiN/HfO2/TiN devices

Recently proposed novel neural network hardware designs imply the use of memristors as electronic synapses in 3D cross-bar architecture. Atomic layer deposition (ALD) is the most feasible technique to fabricate such arrays. In this work, we present the results of the detailed investigation of the gradual resistive switching (memristive) effect in nanometer thick fully ALD grown TiN/HfO2/TiN stacks. The modelling of the I-V curves confirms interface limited trap-assisted-tunneling mechanism along the oxygen vacancies in HfO2 in all conduction states. The resistivity of the stack is found to critically depend upon the distance from the interface to the first trap in HfO2. The memristive properties of ALD grown TiN/HfO2/TiN devices are correlated with the demonstrated neuromorphic functionalities, such as long-term potentiation/depression and spike-timing dependent plasticity, thus indicating their potential as electronic synapses in neuromorphic hardware.

A compound memristive synapse model for statistical learning through STDP in spiking neural networks.

Memristors have recently emerged as promising circuit elements to mimic the function of biological synapses in neuromorphic computing. The fabrication of reliable nanoscale memristive synapses, that feature continuous conductance changes based on the timing of pre- and postsynaptic spikes, has however turned out to be challenging. In this article, we propose an alternative approach, the compound memristive synapse, that circumvents this problem by the use of memristors with binary memristive states. A compound memristive synapse employs multiple bistable memristors in parallel to jointly form one synapse, thereby providing a spectrum of synaptic efficacies. We investigate the computational implications of synaptic plasticity in the compound synapse by integrating the recently observed phenomenon of stochastic filament formation into an abstract model of stochastic switching. Using this abstract model, we first show how standard pulsing schemes give rise to spike-timing dependent plasticity (STDP) with a stabilizing weight dependence in compound synapses. In a next step, we study unsupervised learning with compound synapses in networks of spiking neurons organized in a winner-take-all architecture. Our theoretical analysis reveals that compound-synapse STDP implements generalized Expectation-Maximization in the spiking network. Specifically, the emergent synapse configuration represents the most salient features of the input distribution in a Mixture-of-Gaussians generative model. Furthermore, the network's spike response to spiking input streams approximates a well-defined Bayesian posterior distribution. We show in computer simulations how such networks learn to represent high-dimensional distributions over images of handwritten digits with high fidelity even in presence of substantial device variations and under severe noise conditions. Therefore, the compound memristive synapse may provide a synaptic design principle for future neuromorphic architectures.

Memristor-Based Multithreading

Switch on Event Multithreading (SoE MT, also known as coarse-grained MT and block MT) processors run multiple threads on a pipeline machine, while the pipeline switches threads on stall events (e.g., cache miss). The thread switch penalty is determined by the number of stages in the pipeline that are flushed of in-flight instructions. In this paper, Continuous Flow Multithreading (CFMT), a new architecture of SoE MT, is introduced. In CFMT, a multistate pipeline register (MPR) holds the microarchitectural state of multiple different threads within the execution pipeline stages, where only one thread is active at a time. The MPRs eliminate the need to flush in-flight instructions and therefore significantly improve performance. In recent years, novel memory technologies such as Resistive RAM (RRAM) and Spin Torque Transfer Magnetoresistive RAM (STT-MRAM), have been developed. All of these technologies are nonvolatile, store data as resistance, and can be described as “memristors.” Memristors are power efficient, dense, and fast as compared to standard memory technologies such as SRAM, DRAM, and Flash. Memristors therefore provide the opportunity to place the MPRs physically within the pipeline stages. A performance analysis of CFMT is compared to conventional SoE MT processors, demonstrating up to a 2X performance improvement, while the operational mechanism, due to the use of memristors, is low power and low complexity as compared to conventional SoE MT processors.

A new software paradigm for Internet computing

and depletion in response to polarization reversal in the barrier. The tunneling electrons should experience an extra barrier as long as the semiconductor surface is toggled to depletion, leading to a colossal tunneling electroresistance (Fig. 1). Wen and colleagues epitaxially deposited a 3-nm-thick ultrathin BaTiO3 film with an atomically smooth surface on a Nb-doped SrTiO3 oxide semiconductor and then deposited Pt electrodes on top to form Pt/BaTiO3/Nb:SrTiO3 tunnel junctions. These prototype devices show a tunneling electroresistance two orders greater than the best value ever reported in FTJs. The colossal ON/OFF ratio, low operation voltage (3 V for write and 100 mV for read), reliable switching reproducibility and long data retention suggest great potential for nondestructive readout nonvolatile memories. Moreover, the team observed that the tunneling resistance could be modulated continuously by applying voltage pulses with increasing amplitude due to the continuous tuning on the domain structure in the barrier. This novel FTJ can actually function as a memristor, the adaptive circuit element theoretically predicted 40 years ago but discovered only very recently. The use of memristors may pave the way to future neuromorphic computational architectures. The work by Wen and colleagues not only proposes a promising nonvolatile memory structure with potential to overcome semiconductor devices based on charge storage, but provides tremendous opportunities for innovation in nanoelectronics also.

Integration of nanoscale memristor synapses in neuromorphic computing architectures

Conventional neuro-computing architectures and artificial neural networks have often been developed with no or loose connections to neuroscience. As a consequence, they have largely ignored key features of biological neural processing systems, such as their extremely low-power consumption features or their ability to carry out robust and efficient computation using massively parallel arrays of limited precision, highly variable, and unreliable components. Recent developments in nano-technologies are making available extremely compact and low power, but also variable and unreliable solid-state devices that can potentially extend the offerings of availing CMOS technologies. In particular, memristors are regarded as a promising solution for modeling key features of biological synapses due to their nanoscale dimensions, their capacity to store multiple bits of information per element and the low energy required to write distinct states. In this paper, we first review the neuro- and neuromorphic computing approaches that can best exploit the properties of memristor and scale devices, and then propose a novel hybrid memristor-CMOS neuromorphic circuit which represents a radical departure from conventional neuro-computing approaches, as it uses memristors to directly emulate the biophysics and temporal dynamics of real synapses. We point out the differences between the use of memristors in conventional neuro-computing architectures and the hybrid memristor-CMOS circuit proposed, and argue how this circuit represents an ideal building block for implementing brain-inspired probabilistic computing paradigms that are robust to variability and fault tolerant by design.

Memristor Bridge Synapse-Based Neural Network and Its Learning

Analog hardware architecture of a memristor bridge synapse-based multilayer neural network and its learning scheme is proposed. The use of memristor bridge synapse in the proposed architecture solves one of the major problems, regarding nonvolatile weight storage in analog neural network implementations. To compensate for the spatial nonuniformity and nonideal response of the memristor bridge synapse, a modified chip-in-the-loop learning scheme suitable for the proposed neural network architecture is also proposed. In the proposed method, the initial learning is conducted in software, and the behavior of the software-trained network is learned by the hardware network by learning each of the single-layered neurons of the network independently. The forward calculation of the single-layered neuron learning is implemented on circuit hardware, and followed by a weight updating phase assisted by a host computer. Unlike conventional chip-in-the-loop learning, the need for the readout of synaptic weights for calculating weight updates in each epoch is eliminated by virtue of the memristor bridge synapse and the proposed learning scheme. The hardware architecture along with the successful implementation of proposed learning on a three-bit parity network, and on a car detection network is also presented.