Use Of Dynamic Voltage Scaling Research Articles

A Minimizing Energy Consumption Scheme for Real-Time Embedded System Based on Metaheuristic Optimization

With the widespread application of real-time embedded systems, the contradiction between the energy consumption requirements of modern processors and the limited battery capacity becomes more obvious. Dynamic voltage scaling (DVS) has been proven to be one of the most effective technologies for energy management. However, recent studies have shown that the use of DVS leads to a significant increase in the transient fault rate of processors as the characteristic size of logic gates (or transistors) gets smaller and smaller. In this paper, we consider the problem of assigning processing frequencies to a group of periodic real-time tasks so as to minimize the overall energy consumption under the constraints of time and reliability. Firstly, under the DVS, we take the reliability of the embedded systems into consideration through the regularization terms and present the energy consumption optimization model based on the meta-heuristic algorithms. Secondly, a novel algorithm for adaptive differential whale swarm optimization (ADWOA) is proposed according to the optimization requirements. Finally, the optimized data are saved on the chain through the storable feature of the blockchain for the necessary queries. It is worth noting that the on-chain data contains the intrinsic characteristics of the embedded system, which may give rise to the disclosure of processor privacy. Therefore, we come up with the differential privacy on-chain creating algorithm (DPCA) to protect the privacy of data on the chain. Experimental results show that ADWOA can minimize the energy consumption in real-time embedded system on the premise of ensuring system reliability and privacy.

Instruction-Based Voltage Scaling for Power Reduction in SIMD MPSoCs

Power reduction in Multiprocessor System-on-Chip (MPSoC) is a key design challenge today. In this paper, we present an approach to power reduction for homogeneous SIMD MPSoC platforms. The technique involves the use of dynamic voltage scaling and power management of voltage islands. The basic idea is to have different supply voltage for different instructions: slow instructions run at the higher voltage levels while fast instructions run at lower voltages to save on power. We use a reconfigurable MPSoC architecture, namely MorphoSys, as a vehicle to demonstrate the approach, although the methods are suitable for other SIMD MPSoC architectures. A number of image processing benchmarks are manually mapped to the hardware to demonstrate the power reduction. The results show energy savings from 12% up to 24% for the specified benchmarks using the proposed approach.

Reducing jitter in embedded systems employing a time-triggered software architecture and dynamic voltage scaling

We have previously demonstrated that use of an appropriate dynamic voltage scaling (DVS) algorithm can lead to a substantial reduction in CPU power consumption in systems employing a time-triggered cooperative (TTC) scheduler. In this paper, we consider the impact that the use of DVS has on the levels of both clock and task jitter in TTC applications. We go on to describe a modified DVS algorithm (TTC-jDVS) which can be used where low jitter is an important design consideration. We then demonstrate the effectiveness of the modified algorithm on a data set made up of artificial tasks and in a realistic case study.

A 32-bit PowerPC system-on-a-chip with support for dynamic voltage scaling and dynamic frequency scaling

A PowerPC system-on-a-chip processor which makes use of dynamic voltage scaling and on-the-fly frequency scaling to adapt to the dynamically changing performance demands and power consumption constraints of high-content, battery powered applications is described. The PowerPC core and caches achieve frequencies as high as 380 MHz at a supply of 1.8 V and active power consumption as low as 53 mW at a supply of 1.0 V. The system executes up to 500 MIPS and can achieve standby power as low as 54 /spl mu/W. Logic supply changes as fast as 10 mV//spl mu/s are supported. A low-voltage PLL supplied by an on-chip regulator, which isolates the clock generator from the variable logic supply, allows the SOC to operate continuously while the logic supply voltage is modified. Hardware accelerators for speech recognition, instruction-stream decompression and cryptography are included in the SOC. The SOC occupies 36 mm/sup 2/ in a 0.18 /spl mu/m, 1.8 V nominal supply, bulk CMOS process.

Power-efficient Interconnection Networks: Dynamic Voltage Scaling with Links

Power consumption is a key issue in highperformanceinterconnection network design. Communicationlinks, already a aignificant consumer of power now,will take up an ever larger portion of the power budgetas demand for network bandwidth increases. In this paper,we motivate the use of dynamic voltage scaling (DVS)for links, where the frequency and voltage of links are dynamicallyadjusted to minimize power consumption. Wepropose a history-based DYS algorithm that jjlidiciously adjustsDVS poIicies based on past link utilization. Despitevery conservative assumptions about DVS link characteristics,our approach realizes up to 4.5X power savings (3.2Xaverage), with just an average 27.4% Iatency increase and2.5% throughput reduction. To the best of our knowledge,this is the first study that targets dynamic power optimizationof interconnection networks.