Instruction-Based Voltage Scaling for Power Reduction in SIMD MPSoCs

Abstract

Power reduction in Multiprocessor System-on-Chip (MPSoC) is a key design challenge today. In this paper, we present an approach to power reduction for homogeneous SIMD MPSoC platforms. The technique involves the use of dynamic voltage scaling and power management of voltage islands. The basic idea is to have different supply voltage for different instructions: slow instructions run at the higher voltage levels while fast instructions run at lower voltages to save on power. We use a reconfigurable MPSoC architecture, namely MorphoSys, as a vehicle to demonstrate the approach, although the methods are suitable for other SIMD MPSoC architectures. A number of image processing benchmarks are manually mapped to the hardware to demonstrate the power reduction. The results show energy savings from 12% up to 24% for the specified benchmarks using the proposed approach.