Unused Bits Research Articles

Double-Ended Bit-Stealing for Algebraic Data Types

Algebraic data types are central to the development and evaluation of most functional programs. It is therefore important for compilers to choose compact and efficient representations of such types, in particular to achieve good memory footprints for applications. Algebraic data types are most often represented using blocks of memory where the first word is used as a so-called tag, carrying information about the constructor, and the following words are used for carrying the constructor's arguments. As an optimisation, lists are usually represented more compactly, using a technique called bit-stealing, which, in its simplest form, uses the word-alignment property of pointers to byte-addressed allocated memory to discriminate between the nil constructor (often represented as 0x1) and the cons constructor (aligned pointer to allocated pair). Because the representation supports that all values can be held uniformly in one machine word, possibly pointing to blocks of memory, type erasure is upheld. However, on today's 64-bit architectures, memory addresses (pointers) are represented using only a subset of the 64 bits available in a machine word, which leave many bits unused. In this paper, we explore the use, not only of the least-significant bits of pointers, but also of the most-significant bits, for representing algebraic data types in a full ML compiler. It turns out that, with such a particular utilisation of otherwise unused bits, which we call double-ended bit-stealing, it is possible to choose unboxed representations for a large set of data types, while still not violating the principle of uniform data-representations. Examples include Patricia trees, union-find data structures, stream data types, internal language representations for types and expressions, and mutually recursive ASTs for full language definitions. The double-ended bit-stealing technique is implemented in the MLKit compiler and speedup ranges from 0 to 26 percent on benchmarks that are influenced by the technique. For MLKit, which uses abstract data types extensively, compilation speedups of around 9 percent are achieved for compiling MLton (another Standard ML compiler) and for compiling MLKit itself.

FlexPointer: Fast Address Translation Based on Range TLB and Tagged Pointers

Page-based virtual memory relies on TLBs to accelerate the address translation. Nowadays, the gap between application workloads and the capacity of TLB continues to grow, bringing many costly TLB misses and making the TLB a performance bottleneck. Previous studies seek to narrow the gap by exploiting the contiguity of physical pages. One promising solution is to group pages that are both virtually and physically contiguous into a memory range. Recording range translations can greatly increase the TLB reach, but ranges are also hard to index because they have arbitrary bounds. The processor has to compare against all the boundaries to determine which range an address falls in, which restricts the usage of memory ranges.In this article, we propose a tagged-pointer-based scheme, FlexPointer, to solve the range indexing problem. The core insight of FlexPointer is that large memory objects are rare, so we can create memory ranges based on such objects and assign each of them a unique ID. With the range ID integrated into pointers, we can index the range TLB with IDs and greatly simplify its structure. Moreover, because the ID is stored in the unused bits of a pointer and is not manipulated by the address generation, we can shift the range lookup to an earlier stage, working in parallel with the address generation. According to our trace-based simulation results, FlexPointer can reduce nearly all the L1 TLB misses, and page walks for a variety of memory-intensive workloads. Compared with a 4K-page baseline system, FlexPointer shows a 14% performance improvement on average and up to 2.8x speedup in the best case. For other workloads, FlexPointer shows no performance degradation.

Do not forget the past: A buffer-aided framework for relay based key generation

We address relay-assisted key generation wherein two wireless nodes, that have no direct channel between them, seek the assistance of an intermediate relay to generate secret keys. In a celebrated version of the relay-assisted protocol, as applied by Lai et al., Zhou et al., Wang et al., and Waqas et al., the relay node generates pair-wise keys with the two nodes, and then broadcasts an XOR version of the two keys. Although such protocols are simple and effective, we observe that they face reduction in key rates due to two problems. First, for confidentiality, the relay broadcasts an XOR function of the pair-wise keys thereby pruning the length of the shared key to be the minimum of the key lengths of the pair-wise keys. Secondly, the broadcast phase may also experience outages thereby not being able to share the generated key in every round of the protocol. Identifying these issues, we propose a buffer-aided relaying protocol wherein buffer is used at the relay to store unused secret bits generated in the previous rounds of the protocol so as to provide confidentiality in the subsequent rounds of broadcast. On this buffer-aided protocol, we propose a power-allocation strategy between the phases of key generation and broadcast so as to maximize the throughput and key rate. Rigorous analyses show that buffer-aided relay when implemented along with the proposed power-allocation strategy offer remarkable advantages over existing baselines.

HeapCheck: Low-cost Hardware Support for Memory Safety

Programs written in C/C++ are vulnerable to memory-safety errors like buffer-overflows and use-after-free. While several mechanisms to detect such errors have been previously proposed, they suffer from a variety of drawbacks, including poor performance, imprecise or probabilistic detection of errors, or requiring invasive changes to the ISA, binary-layout, or source-code that results in compatibility issues. As a result, memory-safety errors continue to be hard to detect and a principal cause of security problems. In this work, we present a minimally invasive and low-cost hardware-based memory-safety checking framework for detecting out-of-bounds accesses and use-after-free errors. The key idea of our mechanism is to re-purpose some of the “unused bits” in a pointer in 64-bit architectures to store an index into a bounds information table that can be used to catch out-bounds errors and use-after-free errors without any change to the binary layout. Using this memory-safety checking framework, we enable HeapCheck, a design for detecting Out-of-bounds and Use-after-free accesses for heap-objects, that are responsible for the majority of memory-safety errors in the wild. Our evaluations using C/C++ SPEC CPU 2017 workloads on Gem5 show that our solution incurs 1.5% slowdown on average, using an 8 KB on-chip SRAM cache for caching bounds-information. Our mechanism allows detection of out-of-bounds errors in user-code as well as in unmodified shared-library functions. Our mechanism has detected out-of-bounds accesses in 87 lines of code in the SPEC CPU 2017 benchmarks, primarily in Glibc v2.27 functions, that, to our knowledge, have not been previously detected even with popular tools like Address Sanitizer.

Optimized Design of a Converter Decimal to BCD Encoder and a Reversible 4-bit Controlled Up/Down Synchronous Counter

The field of quantum computing, reversible logic, and nanotechnology have earned much attention from researchers in recent years due to their low power dissipation. Quantum computing has been a guiding light for nanotechnology, optical computing of information, low power CMOS design, computer science. Moreover, the dissipation of energy in the field combina-torial logic circuits becomes one of the most important aspects to be avoided. This problem is remedied by a reversible logic favoring the reproduction of inputs to outputs, which is due to the absence of unused bits. Every bit of information not used generates a loss of information causing a loss of energy under the form of heat, the reversible logic leads to zero heat dissipation. Among the components affected by reversible logic are binary reversible counter and converter from decimal to BCD encoder(D2BE) which are considered essential elements. This article will propose an optimized reversible design of a converter from decimal to BCD encoder (D2BE) and an optimized design of reversible Binary counter with up/ down. Our designs show an improvement compared to previous works by replacing some reversible gates with others while keeping the same functionality and improving performance criteria in terms of the number of gates, garbage outputs, constant inputs, quantum cost, delay, and Hardware complexity.

Reliable and Energy Efficient MLC STT-RAM Buffer for CNN Accelerators

We propose a lightweight scheme where the formation of a data block is changed in such a way that it can tolerate soft errors significantly better than the baseline. The key insight behind our work is that CNN weights are normalized between -1 and 1 after each convolutional layer, and this leaves one bit unused in half-precision floating-point representation. By taking advantage of the unused bit, we create a backup for the most significant bit to protect it against the soft errors. Also, considering the fact that in MLC STT-RAMs the cost of memory operations (read and write), and reliability of a cell are content-dependent (some patterns take larger current and longer time, while they are more susceptible to soft error), we rearrange the data block to minimize the number of costly bit patterns. Combining these two techniques provides the same level of accuracy compared to an error-free baseline while improving the read and write energy by 9% and 6%, respectively.

Defending Against Flush+Reload Attack With DRAM Cache by Bypassing Shared SRAM Cache

Cache side-channel attack is one of the critical security threats to modern computing systems. As a representative cache side-channel attack, Flush+Reload attack allows an attacker to steal confidential information (e.g., private encryption key) by monitoring a victim’s cache access patterns while generating the confidential values. Meanwhile, for providing high performance with memory-intensive applications that do not fit in the on-chip SRAM-based last-level cache (e.g., L3 cache), modern computing systems start to deploy DRAM cache between the SRAM-based last-level cache and the main memory DRAM, which can provide low latency and/or high bandwidth. However, in this work, we propose an approach that exploits the DRAM cache for security rather than performance, called ByCA . ByCA bypasses the L3 shared cache when accessing cache blocks suspected as target blocks of an attacker. Consequently, ByCA eliminates the timing difference when the attacker accesses the target cache blocks, nullifying the Flush+Reload attacks. To this end, ByCA keeps cache blocks suspected as target blocks of the attacker and stores their states (i.e., flushed by clflush or not) in the L4 DRAM cache even with clflush instruction; ByCA re-defines and re-implements clflush instruction not to flush cache blocks from the L4 DRAM cache while flushing the blocks from other level caches (i.e., L1, L2, and L3 caches). In addition, ByCA bypasses L3 cache when the attacker or the victim accesses the target blocks flushed by clflush , making the attacker always obtain the blocks from L4 DRAM cache regardless of the victim’s access patterns. Consequently, ByCA eliminates the timing difference, thus the attacker cannot monitor the victim’s cache access patterns. For L4 DRAM cache, we implement Alloy Cache design and use an unused bit in a tag entry for each block to store its state. ByCA only requires a single bit extension to cache blocks in L1 and L2 private caches, and a tag entry for each block in the L4 DRAM cache. Our experimental results show that ByCA completely eliminates the timing differences when the attacker reloads the target blocks. Furthermore, ByCA does not show the performance degradation for the victim while co-running with the attacker that flushes and reloads target blocks temporally and repetitively.

Experimental and numerical analysis of rotary tricone drill bit and its wear prediction

In this study, a three-dimensional model of unused drilling bit was prepared in CAD design modular and analyzed using the ANSYS workbench. Static and fatigue analysis was carried out, and wear-affected area was investigated through FEM. From the analysis, the maximum deformation and maximum von Mises stress obtained are 0.019492 mm and 435.11 MPa, respectively. During fatigue analysis, the minimum tool life was obtained as 2084.9 cycle life. During the microstructure analysis, wear phenomenon such as plastic deformation is visible at a higher magnification of 600× . Crack is visible at a lower magnification 200× . Furthermore, EDX analysis has also been done on samples prepared from unused and used tricone drilling bit. A higher variation of carbon (C) content by weight percentage of unused and used tricone drilling bit was observed which indicates reducing ductility and malleability of the material.

EFFICIENT SECURITY FRAMEWORK FOR DATA INTEGRITY AND DATA ACCESS IN CLOUD ENVIRONMENT

Cloud computing is a highly emerging area in the market and provide the way of mechanism for global challengers. The priority of Confidentiality, Integrity, Availability, Authenticity, and Privacy are essential concerns for both Cloud providers and consumers.This paper attempts a combination of cryptography andsteganography, which provides a big determination for its security. The secret message can be encrypted before its actual process. The main goal of this work to hide a secret message into pixels of the image so that the hacker does not difference between the original and steganography image.The embedding can be using LSB techniques. Steganography can be replaced by unused bits in the data (such as graphics, sound, audio, video, text). The existing work, AES algorithm can be used to cryptography. The hackers can easily to theft the information due to the insecure links. To overcome this problem to implement the F5 matrix encoding to improve the efficiency of embedding. This present work focuses on enlarge the technique to secure text, video, audio, image with authenticity and integrity.

Cluster-Based Opportunistic Spectrum Allocation in CRWMN’s Using Co-operative Mechanism

With the innovation of Cognitive Radio Wireless Mesh Network’s, Opportunistic Spectrum Allocation can possibly moderate spectrum lack, by letting Secondary User’s a chance to sense and use unused bits of opportunistic licensed spectrum without any unfavourable effect on the Primary User’s. In Cognitive Radio Wireless Mesh Network’s, the Medium-Access-Control protocols characterizes the utilization of spectrum proficiently by allocating the channels among the users. Majority of proposed Medium-Access-Control protocols are utilizing Common-Control-Channel for dealing with the assets of Secondary-Users. The major downsides of these Medium-Access-Control protocols are broadcasting of Control-channel when substantial number of Secondary-User exists. In contrast with these Medium-Access-Control protocols, we develop an algorithm Time-Slotted-Allocation-Medium-Access-Control (TSA-MAC) protocol which is based on Clustered Time-Division-Medium-Access approach, which permits Secondary-User’s to allocate opportunistic spectrum with the help of co-operative decisions by exchange control information. In this approach, we are dividing the channels as different slots on which Secondary-User’s can transfer control and data packets. The TSA-MAC protocol will enhance the throughput for the Secondary-User’s over the communication channel. And also this method will facilitate to decide and allocate free channels for Secondary-User’s without interfering with Primary User’s.

RFC: Range feature code for TCAM-based packet classification

Packet classification has been widely used in various Internet applications, including the recent hot topic SDN. Generally, TCAM is a typical device for high-speed packet classification. However, when it comes to some classification rules that contain ranges, since TCAM is not well designed to represent ranges, range expansion problem is caused. Range expansion could cost much more TCAM entries than the number of rules, thus impairing the utilization of TCAM. In practice, there are some unused bits in a TCAM entry, which could be used to reduce the range expansion. In this paper, we propose a scheme to efficiently represent ranges with such extra bits. Our scheme is based on the observation that in prior encoding schemes that use extra bits to represent ranges, the encoding in extra bits and its fallback scheme are always regarded as two totally separate processes. Even though the two encoding methods are different, as they both focus on the same rule, there actually exists some relevance in information of the two encoding process. In our scheme, the two encoding processes are brought together with range feature code (RFC) as the link, thus reducing the information redundancy between them. Experiment results show that when 36 extra bits are available in TCAM, our scheme reduces the redundancy of range rules by around 36% compared with the best prior scheme.

隐形ACK:片上网络ACK包的隐形传输

Network-on-Chip (NoC) is a promising replacement of bus architecture due to its better scalability. In state-of-the-art NoCs, each packet contains several fixed-length flits, which facilitates allocations of network resources but brings in many unused bits. In this paper, we propose a novel technique called Stealth-ACK to effectively address the above problem. Stealth-ACK leverages unused bits in head flits of non-ACK packets to carry and stealthily transmit ACK information. Such stealth transmissions of ACK information effectively reduce not only the amount of dedicated ACK packets on NoC, but also the number of unused bits in head flits of non-ACK packets, which significantly reduces wastes on NoC bandwidth. Experimental results show that Stealth-ACK averagely increases the throughput of 16 × 16 2-D mesh NoC by 11.9%, and averagely reduces the NoC latency by 34.8% on application traces of SPLASH-2. Moreover, Stealth-ACK only requires trivial hardware modification to basic router architectures, which incurs negligible power consumption and area cost.

A soft error tolerant register file for highly reliable microprocessor design

Dealing with radiation-induced soft errors is of the main design challenges in today's nanometer design of embedded systems especially in safety critical applications. Register file is a vulnerable section of a microprocessor that needs to be protected against soft errors. This paper proposes a soft error tolerant structure for the register file of the safety-critical embedded processors. In this structure, the double modular redundancy (DMR) technique based on a new hardware implementation is employed for the normal values. Moreover, the unused bits of the registers are used to be further redundant for the used ones for the narrow-width values. We show that the proposed structure offers much more reliability improvement in comparison with the conventional techniques for protection of register files such as DMR, triple modular redundancy and error detection and correction solutions based on Hamming code.

Resource Utilization in Cloud Computing using Hybrid Algorithm

Objectives: The proposed algorithm represents a multivariate selection and security mechanism for the data which has to be kept at the cloud server. The paper also focuses on the prioritization of the data so that for a given span of time data with high priority is processed first. Methods/Statistical Analysis: The paper has presented a unique way to select encryption algorithm so that miss-utilization is prevented. The paper has included lattice based encryption NTRU (N-th degree Truncated Polynomial Ring Unit) and key based encryption for the security of data. Findings: The unused data bits have been optimized using GA (Genetic Algorithm) and the results have been calculated in terms of total number of completed jobs with priority and the CPU Utilization made against the Jobs. Application/Improvements: Resources which will be utilized at the cloud server would cost the user with some amount but there is optimization of resources in terms of CPU utilization and job completion.

RESI: Register-Embedded Self-Immunity for Reliability Enhancement

Technology scaling in the nano-CMOS era has reached a point where coping with the failures produced by soft errors has become one of the key challenges when it comes to reliability. Akin to the fact that a register file is accessed more frequently than any other architectural component, register file protection is imperative to obstruct errors from propagating throughout a computing system. Furthermore, negative bias temperature instability (NBTI) has emerged as a major concern due to its negative impact on the lifetime of pMOS devices. Indeed, many of the pMOS transistors most affected by NBTI are in the register files as they are implemented as SRAM, which are particularly vulnerable due to their small structure size. Based on our observation that some register bits are not continuously used to represent a value stored in a register, we present a technique that exploits unused bits to improve the register file immunity against soft errors and mitigate NBTI effects. We show that our technique can reduce, on average, the register file vulnerability against multiple bit upsets by 97% (up to 100%), resulting in a high system fault coverage under various scenarios, while consuming less power and still occupying a similar area footprint compared to protecting the register file against single bit upsets (SBUs) only. The achieved result is 63% better compared to the state-of-the-art in register file protection. To compare and quantify the effect of our technique, we observe its impact on the processor's temperature using an infrared thermal camera and show that, due to consuming less power per area, our technique also operates at a lower temperature compared to protecting the register file against SBUs only. Finally, we investigate how our technique additionally moderates the stress induced by NBTI in register file SRAM cells.

A CASE FOR HYBRID INSTRUCTION ENCODING FOR REDUCING CODE SIZE IN EMBEDDED SYSTEM-ON-CHIPS BASED ON RISC PROCESSOR CORES

Embedded computing differs from general purpose computing in several aspects. In most embedded systems, size, cost and power consumption are more important than performance. In embedded System-on-Chips (SoC), memory is a scarce resource and it poses constraints on chip space, cost and power consumption. Whereas fixed instruction length feature of RISC architecture simplifies instruction decoding and pipeline implementation, its undesirable side effect is code size increase caused by large number of unused bits. Code size reduction minimizes memory size, chip space and power consumption all of which are significant for low power portable embedded systems. Though code size reduction has drawn the attention of architects and developers, the solutions currently used are more of cure than of prevention. Considering the huge number of embedded applications, there is a need for a dedicated processor optimized for low power and portable embedded systems. In the study, we propose a variation of Hybrid Instruction Encoding (HIE) for the embedded processors. Our scheme uses fixed number of multiple instruction lengths with provision for hybrid sizes for the offset and the immediate fields thereby reducing the number of unused bits. We simulated the HIE for the MIPS32 processors and measured code sizes of various embedded applications of MiBench and MediaBench benchmarks using an offline tool developed newly. We noticed up to 27% code reduction for large and medium sized embedded applications respectively. This results in reduction of on-chip memory capacity up to 1 mega bytes that is very significant for SoC based embedded applications. Considering the large market share of embedded systems, it is worth investing in a new architecture and development of dedicated HIE-RISC processor cores for portable embedded systems based on SoCs.

An Efficient Hybrid Image Coding Scheme Combining Wavelets, Neural Networks and Differential Pulse Code Modulation for Effectual Image Compression

Large images consume more storage space needing high data rates for transmission demanding the innovation of efficient image compression systems. Owing to the massive parallel architecture and generalization ability of neural networks to memorize inputs even on untrained data, the computational simplicity of wavelets, ability of Differential Pulse Code Modulation (DPCM) to reduce the unused or redundant bits in the information, in this paper an hybrid image compression system combining the advantages of wavelets and neural networks is implemented along with Differential Pulse Code Modulation based on the predicted sample values. Scalar quantization and Huffman encoding schemes are used as well for compressing different sub bands i.e the low frequency band coefficients are compressed by the DPCM while the high frequency band coefficients are compressed using neural networks. Satisfactory reconstructed images with increased bit rates and large Peak Signal to Noise Ratio (PSNR) can be achieved with this scheme. Wavelet transform eliminates the blocking artefacts’ associated with cosine transform and neural networks minimize the Mean Square Error (MSE).Empirical analysis and metrics calculation is performed for the sake of relative analysis. General Terms Artificial Neural Networks, Fidelity, Mean Square Error, Peak Signal to Noise Ratio, Quantization and Huffman encoding.

Enhanced Duplication: a Technique to Correct Soft Errors in Narrow Values

Soft errors are transient errors that can alter the logic value of a register bit causing data corruption. They can be caused by radiation particles such as neutrons or alpha particles. Narrow values are commonly found in the data consumed or produced by processors. Several techniques have recently been proposed to exploit the unused bits in narrow values to protect them against soft errors. These techniques replicate the narrow value over the unused register bits such that errors can be detected when the value is duplicated and corrected when the value is tripled. In this letter, a technique that can correct errors when the narrow value is only duplicated is presented. The proposed approach stores a modified duplicate of the narrow value such that errors on the original value and the duplicate can be distinguished and therefore corrected. The scheme has been implemented at the circuit level to evaluate its speed and also at the architectural level to assess the benefits in correcting soft errors. The results show that the scheme is significantly faster than a parity check and can improve substantially the number of soft errors that are corrected compared to existing techniques.

Huffman-based code compression techniques for embedded processors

The size of embedded software is increasing at a rapid pace. It is often challenging and time consuming to fit an amount of required software functionality within a given hardware resource budget. Code compression is a means to alleviate the problem by providing substantial savings in terms of code size. In this article we introduce a novel and efficient hardware-supported compression technique that is based on Huffman Coding. Our technique reduces the size of the generated decoding table, which takes a large portion of the memory. It combines our previous techniques, Instruction Splitting Technique and Instruction Re-encoding Technique into new one called Combined Compression Technique to improve the final compression ratio by taking advantage of both previous techniques. The instruction Splitting Technique is instruction set architecture (ISA)-independent. It splits the instructions into portions of varying size (called patterns) before Huffman coding is applied. This technique improves the final compression ratio by more than 20% compared to other known schemes based on Huffman Coding. The average compression ratios achieved using this technique are 48% and 50% for ARM and MIPS, respectively. The Instruction Re-encoding Technique is ISA-dependent. It investigates the benefits of reencoding unused bits (we call them reencodable bits) in the instruction format for a specific application to improve the compression ratio. Reencoding those bits can reduce the size of decoding tables by up to 40%. Using this technique, we improve the final compression ratios in comparison to the first technique to 46% and 45% for ARM and MIPS, respectively (including all overhead that incurs). The Combined Compression Technique improves the compression ratio to 45% and 42% for ARM and MIPS, respectively. In our compression technique, we have conducted evaluations using a representative set of applications and we have applied each technique to two major embedded processor architectures, namely ARM and MIPS.

Bandwidth Analysis of Functional Interconnects Used as Test Access Mechanism

Test data travels through a System on Chip (SOC) from the chip pins to the Core-Under-Test (CUT) and vice versa via a Test Access Mechanism (TAM). Conventionally, a TAM is implemented using dedicated communication infrastructure. However, also existing functional interconnect, such as a bus or Network on Chip (NOC), can be reused as TAM; this will reduce the overall design effort and associated silicon area. For a given core, its test set, and maximal bandwidth that the functional interconnect can offer between test equipment and core-under-test, our approach instantiates a test wrapper for the core-under-test such that the test length is minimized. Unfortunately, it is unavoidable that along with the test data also unused (idle) bits are transported. This paper presents a holistic TAM bandwidth under-utilization analysis when functional interconnect is considered for test data transportation. We classify the idle bits into four types that refer to the root-cause of bandwidth under-utilization and pinpoint design improvement opportunities. Experimental results show an average bandwidth utilization of 80%, while the remaining 20% is consumed by the idle bits.