Unselected Wordlines Research Articles

Page Type-Aware Data Migration Technique for Read Disturb Management of NAND Flash Memory

Read disturb is a phenomenon in which the cells of all unselected wordlines (WLs) within a block are soft programed while reading a selected WL, which causes errors. To solve the problem of read disturb, read reclaim (RR) operations, which migrate deteriorated block data to a new free block, are executed when the read count of the deteriorated block exceeds a preset threshold. RR requires additional operations, such as error correction, reprogramming, block erasure, and occupying I/O. So as the number of RR operations increases, the performance and reliability of the memory degrade. We observe that read disturb affects pages within a block differently according to page types. With this perspective, we propose Page Type-aware Data Migration technique (PTDM) technique, which migrates pages within blocks according to the vulnerability to read disturb. Shifting RR from the conventional block level to the page level improves the efficiency of the memory by reducing data migration. Also, we propose distributing read-hot data into several blocks during migration to reduce read disturb impact. Our experimental results show that the proposed method can reduce the amount of RR data migration and the overall erasure counts by 39.53% and 21.69%, respectively.

A new bias scheme for a low power consumption ReRAM crossbar array

This paper proposes a new bias scheme for a crossbar array that can improve the power consumption and read margin. The concept of the newly proposed 5/12 bias scheme is to reduce the bias of the unselected cells for power consumption and the bias of half-selected cells for a reduced line voltage drop of the selected cell. In the 5/12 bias scheme, the unselected word line and bit line are biased to 5 × Vapp/12 and 7 × Vapp/12, respectively. The electrical characteristics of the 5/12 bias scheme are evaluated by HSPICE simulations and it is found that appropriate nonlinearity of selector can simultaneously achieve low power consumption and high read margin for 5/12 bias scheme.

A Bit-by-Bit Re-Writable Eflash in a Generic 65 nm Logic Process for Moderate-Density Nonvolatile Memory Applications

Embedded nonvolatile memory (eNVM) is considered to be a critical building block in future system-on-chip and microprocessor systems. Various eNVM technologies have been explored for high-density applications including dual-poly embedded flash (eflash), FeRAM, STT-MRAM, and RRAM. On the other end of the spectrum, logic-compatible eNVM such as e-fuse, anti-fuse, and single-poly eflash memories have been considered for moderate-density low-cost applications. In particular, single-poly eflash memory has been gaining momentum as it can be implemented in a generic logic process while supporting multiple program-erase cycles. One key challenge for single-poly eflash is enabling bit-by-bit re-write operation without a boosted bitline voltage as this could cause disturbance issues in the unselected wordlines. In this work, we present details of a bit-by-bit re-writable eflash memory implemented in a generic 65 nm logic process which addresses this key challenge. The proposed 6 T eflash memory cell can improve the overall cell endurance by eliminating redundant program/erase cycles while preventing disturbance issues in the unselected wordlines. We also provide details of special high voltage circuits such as a voltage-doubler based charge pump circuit and a multistory high-voltage switch, for generating a reliable high-voltage output without causing damage to the standard logic transistors.

Design of Unique NAND Flash Memory Cells with Low Program Disturbance Utilizing Novel Booster Line

Unique NAND flash memory cells with a booster line structure were designed to increase the channel voltage of a program-inhibited cell during program cycles. When a program voltage was applied to the selected word line, booster-line voltage coupled with control gate potential induced a high voltage in a program-inhibited channel. Because the turning on of the unselected cells was initiated by the booster line during programming, an unselected word line was maintained in the floating state without applying a pass voltage. Program disturbance in the NAND flash memory cell was decreased using a booster-line boosting scheme, and the cell's pass disturbance was effectively eliminated. The proposed unique NAND flash memory cell with a booster line can be used to improve the reliability of nanoscale NAND flash memories.

0.13 µm Metal-Oxide-Nitride-Oxide-Semiconductor Single Transistor Memory Cell with Separated Source Line

A 0.13 µm metal (conductive gate) oxide nitride oxide semiconductor (MONOS) single transistor memory cell is proposed and demonstrated. The three main limiting factors and their solutions in a 0.13 µm MONOS single transistor memory cell with a separated source line are clarified. The first issue is the reduction in the margin of program inhibit voltage due to a short channel effect. This problem can be improved by applying a positive bias voltage to unselected wordlines. The second issue is the leakage current from unselected cells. This problem can be reduced by the use of a source bias read technique. The third issue is the read disturb of a selected cell. This problem can be improved with a thicker tunnel insulator without increase in program time. An experimental 0.13 µm MONOS memory cell is obtained with satisfactory results. A small cell size of about 6F2 (F: feature size) is proposed by the use of winding source lines.

Noncomplimentary rewriting and serial-data coding scheme for shared-sense-amplifier open-bit-line DRAM

A noncomplimentary rewriting scheme is proposed for open-bit-line DRAM's adopting a shared subsense amplifier. The scheme can theoretically cancel inter-bit-line coupling noise down to zero. In order to suppress the peak in unselected word line noise, a serial-data coding scheme was also developed, This scheme can reduce unselected word-line noise by at least 50%.

Diode access matrix performance

A circuit analysis of diode access matrices is presented. The problem is reduced to manageable proportions through a series of equivalent circuits, without neglecting any essential features. The voltage waveforms on selected and unselected word and diode rails are derived. For low access noise, it is of paramount importance to have the access matrix power supply ideally floating with respect to its surroundings. If that is the case, the access noise due to the voltage bounces on half-selected and unselected word lines cancel out one another, and the total access noise is, to a first approximation, zero. The residual access noise observed in practical memories must, therefore, be the result of second-order effects attributable to time delays along the bit lines, stray impedances, etc. Experimental measurements on a simulated 22 by 22 access matrix and a 512- word by 96-bit plated wire memory plane gave results in good agreement with those calculated. This analysis provides an appreciation of the effect of each individual design parameter on the overall performance of diode access matrices.