Diode access matrix performance

Abstract

A circuit analysis of diode access matrices is presented. The problem is reduced to manageable proportions through a series of equivalent circuits, without neglecting any essential features. The voltage waveforms on selected and unselected word and diode rails are derived. For low access noise, it is of paramount importance to have the access matrix power supply ideally floating with respect to its surroundings. If that is the case, the access noise due to the voltage bounces on half-selected and unselected word lines cancel out one another, and the total access noise is, to a first approximation, zero. The residual access noise observed in practical memories must, therefore, be the result of second-order effects attributable to time delays along the bit lines, stray impedances, etc. Experimental measurements on a simulated 22 by 22 access matrix and a 512- word by 96-bit plated wire memory plane gave results in good agreement with those calculated. This analysis provides an appreciation of the effect of each individual design parameter on the overall performance of diode access matrices.