Unreliable Bits Research Articles

XED

Large-granularity memory failures continue to be a critical impediment to system reliability. To make matters worse, as DRAM scales to smaller nodes, the frequency of unreliable bits in DRAM chips continues to increase. To mitigate such scaling-related failures, memory vendors are planning to equip existing DRAM chips with On-Die ECC. For maintaining compatibility with memory standards, On-Die ECC is kept invisible from the memory controller. This paper explores how to design high reliability memory systems in presence of On-Die ECC. We show that if On-Die ECC is not exposed to the memory system, having a 9-chip ECC-DIMM (implementing SECDED) provides almost no reliability benefits compared to an 8-chip non-ECC DIMM. We also show that if the error detection of On-Die ECC can be exposed to the memory controller, then Chipkill-level reliability can be achieved even with a 9-chip ECC-DIMM. To this end, we propose e<u>X</u>posed On-Die <u>E</u>rror <u>D</u>etection (XED) , which exposes the On-Die error detection information without requiring changes to the memory standards or consuming bandwidth overheads. When the On-Die ECC detects an error, XED transmits a pre-defined "catch-word" instead of the corrected data value. On receiving the catch-word, the memory controller uses the parity stored in the 9-chip of the ECC-DIMM to correct the faulty chip (similar to RAID-3). Our studies show that XED provides Chipkill-level reliability (172x higher than SECDED), while incurring negligible overheads, with a 21% lower execution time than Chipkill. We also show that XED can enable Chipkill systems to provide Double-Chipkill level reliability while avoiding the associated storage, performance, and power overheads.

Highly Reliable Spin-Transfer Torque Magnetic RAM-Based Physical Unclonable Function With Multi-Response-Bits Per Cell

Memory-based physical unclonable function (MemPUF) has gained tremendous popularity in the recent years to securely preserve secret information in computing systems. Most MemPUFs in the literature have unreliable bit generation and/or are incapable of generating more than one response-bit per cell. Hence, we propose a novel MemPUF exploiting the unique characteristics of spin-transfer torque magnetic RAM (STT-MRAM) that can overcome these issues. Bit generation in our STT-MRAM-based MemPUF is stabilized using a novel automatic write-back technique. In addition, the alterability of the magnetic tunneling junction state is exploited to expand the response-bit capacity per cell. Our analysis demonstrated the advantage of our scheme in reliability enhancement (bit-error rate from $\sim 10^{-1}$ to $\sim 10^{-6}$ in the worst case under varying conditions) and response-bit capacity per cell improvement (from 1 to 1.48 bit). In comparison with the conventional MemPUFs, our approach is also better in terms of the average chip area and energy for producing a response-bit.

Synergistic High Charge-Storage Capacity for Multi-level Flexible Organic Flash Memory.

Electret and organic floating-gate memories are next-generation flash storage mediums for printed organic complementary circuits. While each flash memory can be easily fabricated using solution processes on flexible plastic substrates, promising their potential for on-chip memory organization is limited by unreliable bit operation and high write loads. We here report that new architecture could improve the overall performance of organic memory, and especially meet high storage for multi-level operation. Our concept depends on synergistic effect of electrical characterization in combination with a polymer electret (poly(2-vinyl naphthalene) (PVN)) and metal nanoparticles (Copper). It is distinguished from mostly organic nano-floating-gate memories by using the electret dielectric instead of general tunneling dielectric for additional charge storage. The uniform stacking of organic layers including various dielectrics and poly(3-hexylthiophene) (P3HT) as an organic semiconductor, followed by thin-film coating using orthogonal solvents, greatly improve device precision despite easy and fast manufacture. Poly(vinylidene fluoride-trifluoroethylene) [P(VDF-TrFE)] as high-k blocking dielectric also allows reduction of programming voltage. The reported synergistic organic memory devices represent low power consumption, high cycle endurance, high thermal stability and suitable retention time, compared to electret and organic nano-floating-gate memory devices.

39 fJ/bit On-Chip Identification ofWireless Sensors Based on Manufacturing Variation

A 39 fJ/bit IC identification system based on FET mismatch is presented and implemented in a 130 nm CMOS process. ID bits are generated based on the ΔVT between identically drawn NMOS devices due to manufacturing variation, and the ID cell structure allows for the characterization of ID bit reliability by characterizing ΔVT . An addressing scheme is also presented that allows for reliable on-chip identification of ICs in the presence of unreliable ID bits. An example implementation is presented that can address 1000 unique ICs, composed of 31 ID bits and having an error rate less than 10-6, with up to 21 unreliable bits.

Iterative Soft-Decision Decoding of Hermitian Codes

This paper proposes an iterative soft-decision decoding algorithm for one of the most popular algebraic-geometric (AG) codes - Hermitian codes. The algorithm is designed by integrating the two most powerful soft-decision decoding algorithms, the adaptive belief propagation (ABP) algorithm and the Koetter-Vardy (KV) list decoding algorithm. The ABP algorithm performs iterative decoding based on an adapted parity-check matrix of a Hermitian code to enhance the reliability of the soft received information. With the enhanced reliability, the KV algorithm performs soft-decision list decoding to obtain the original message. Since the matrix adaptation relies on bit reliabilities, regrouping of the unreliable bits is introduced to assist the ABP decoding. A complexity reducing ABP-KV decoding approach is proposed based on assessing the soft information provided by the ABP algorithm and determining whether the following KV decoding steps should be carried out. Geometric interpretation of the ABP algorithm is presented, demonstrating the necessity of performing matrix adaptation. Our performance analysis shows the proposed iterative decoding algorithm outperforms both the existing decoding approaches for Hermitian codes and the ABP-KV decoding of Reed-Solomon (RS) codes.

Restoration of embedded image from corrupted stego image

Digital images are easily corrupted by noise during transmission. This paper presents a robust method for restoring embedded image from corrupted stego image. We firstly identify unreliable bits of each pixel in the embedded image by detecting noise in the stego image. Secondly, we calculate the distortion value and credibility value of each pixel, and use them to determine corrupted pixels. For each corrupted pixel, we correct its value by adjusting the unreliable bits. Experimental results show that the proposed method can restore embedded image with good visual quality.

IDMA-based cooperative partial packet recovery: principles and applications

In this article, we focus on the cooperative multi-user network model and propose a relay-assisted partial packet recovery scheme in which asynchronous interleave-division multiple-access (IDMA) with iterative chip-by-chip multiuser detection (MUD) is used for the recovery of partial packets from multiple sources. In packet transmission, only a few erroneous bits may cause the entire packet to be discarded and partial packet recovery can reduce waste in resource by retransmitting only the bits that are unreliable, As the retransmitted partial packets for different sources can be of different lengths, IDMA is particularly suitable because of the simplicity of chip-by-chip MUD and because there is no need for strict synchronization. Our detailed scheme, which includes a feedback request strategy for indicating the unreliable bits, is presented and its performance is investigated. The simulation results show that the network throughput can be significantly improved by the proposed scheme, compared to traditional CDMA-based automatic repeat request (ARQ). Moreover, under the context of cognitive radio networks, we propose a hybrid strategy in which interleave division multiplexing (IDM) is used during whole-packet retransmission, and demonstrate the effectiveness of the proposed scheme with and without the hybrid strategy as well as give insights about the throughput performance under different parameter settings.

Threshold-Based Relaying in Coded Cooperative Networks

In cooperative communications, error propagation at the relay nodes degrades the diversity order of the system. To combat that effect, we present a novel technique to control error propagation at the relays, which is implemented in the context of a distributed turbo code. In the presented technique, the relay calculates the log-likelihood ratio (LLR) values for the bits sent from the source. These values are subjected to a threshold to distinguish the reliable bits from the unreliable bits. The relay then forwards the bits that are deemed reliable and discards the bits that are not, resulting in fewer errors propagating to the destination. The assumption here is that the destination does not know the location of the discarded bits. We develop upper bounds on the end-to-end bit error rate, enabling us to optimize the threshold in terms of the minimum end-to-end bit error rate. We compare our technique with existing techniques that have been proposed to control error propagation, including using only a cyclic redundancy code check at the relay, forwarding analog LLR values, and by employing no error control at the relay at all. We demonstrate, through several numerical examples, that the proposed scheme outperforms all existing schemes.

CRC-assisted error correction in a convolutionally coded system

In communication systems employing a serially concatenated cyclic redundancy check (CRC) code along with a convolutional code (CC), erroneous packets after CC decoding are usually discarded. The list Viterbi algorithm (LVA) and the iterative Viterbi algorithm (IVA) are two existing approaches capable of recovering erroneously decoded packets. We here employ a soft decoding algorithm for CC decoding, and introduce several schemes to identify error patterns using the posterior information from the CC soft decoding module. The resultant iterative decoding-detecting (IDD) algorithm improves error performance by iteratively updating the extrinsic information based on the CRC parity check matrix. Assuming errors only happen in unreliable bits characterized by small absolute values of the log-likelihood ratio (LLR), we also develop a partial IDD (P-IDD) alternative which exhibits comparable performance to IDD by updating only a subset of unreliable bits. We further derive a soft-decision syndrome decoding (SDSD) algorithm, which identifies error patterns from a set of binary linear equations derived from CRC syndrome equations. Being noniterative, SDSD is able to estimate error patterns directly from the decoder output. The packet error rate (PER) performance of SDSD is analyzed following the union bound approach on pairwise errors. Simulations indicate that both IDD and IVA are better tailored for single parity check (PC) codes than for CRC codes. SDSD outperforms both IDD and LVA with weak CC and strong CRC. Applicable to AWGN and flat fading channels, our algorithms can also be extended to turbo coded systems.

Reliability-Based Hybrid ARQ Scheme with Encoded Parity Bit Retransmissions and Message Passing Decoding

Reliability-based hybrid ARQ (RB-HARQ) is a kind of incremental-redundancy ARQ recently introduced. In the RB-HARQ, the receiver returns both NAK signal and set of unreliable bit indices if the received sequence is not accepted. Since each unreliable bit index is determined by the bitwise posterior probability, better approximation of that probability becomes crucial as the number of retransmissions increases. Assuming the systematic code for the initial transmission, the proposed RB-HARQ scheme has the following two features: (a) the sender retransmits newly encoded and interleaved parity bits corresponding to the unreliable information bits; (b) the retransmitted parity bits as well as the initial received sequence are put all together to perform the message passing decoding i.e. the suboptimal MAP decoding. Finally, simulation results are shown to evaluate the above two features.

Algebraic Soft-Decision Decoding of Reed-Solomon Codes with Erasures on Gaussian Channels

The search for increasing the error performance of algebraic soft-decision decoding of high rate Reed-Solomon (RS) codes motivates the development of this work in an attempt to determine the ultimate error-correcting capabilities of algebraic soft-decision decoding of RS codes in Gaussian channels with erasures. It is shown through simulation that a significant performance improvement can be obtained when the unreliable bits received from channel output are declared as erased bits. An alternative method to construct the reliability matrix is developed through the mapping of the a posteriori channel probabilities in order to assign equal multiplicity for symbols with the same erased bits patterns. Conversely, it is also shown through simulation that trying to declare the unreliable symbols received from the channel as erasures does not lead to any performance gain and in some cases it would affect the decoder performance.

Reliability-based hybrid ARQ

A new hybrid automatic repeat request (ARQ) scheme that utilises reliability estimates generated by soft-input, soft-output (SISO) decoders is proposed. The proposed ARQ scheme transmits additional information for the unreliable bits, and this information is used to perform additional decoding. Results are presented that show this ARQ technique can provide performance close to the channel capacity.

High rate concatenated coding systems using bandwidth efficient trellis inner codes

High-rate concatenated coding systems with bandwidth-efficient trellis inner codes and Reed-Solomon (RS) outer codes are investigated for application in high-speed satellite communication systems. Two concatenated coding schemes are proposed. In one the inner code is decoded with soft-decision Viterbi decoding, and the outer RS code performs error-correction-only decoding (decoding without side information). In the other the inner code is decoded with a modified Viterbi algorithm, which produces reliability information along with the decoded output. In this algorithm, path metrics are used to estimate the entire information sequence, whereas branch metrics are used to provide reliability information on the decoded sequence. This information is used to erase unreliable bits in the decoded output. An errors-and-erasures RS decoder is then used for the outer code. The two schemes have been proposed for high-speed data communication on NASA satellite channels. The rates considered are at least double those used in current NASA systems, and the results indicate that high system reliability can still be achieved.< <ETX xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">&gt;</ETX>