Universal Transceiver Research Articles

Universal Transceivers: Opportunities and Future Directions for the Internet of Everything (IoE)

The Internet of Everything (IoE) is a recently introduced information and communication technology (ICT) framework promising for extending the human connectivity to the entire universe, which itself can be regarded as a natural IoE, an interconnected network of everything we perceive. The countless number of opportunities that can be enabled by IoE through a blend of heterogeneous ICT technologies across different scales and environments and a seamless interface with the natural IoE impose several fundamental challenges, such as interoperability, ubiquitous connectivity, energy efficiency, and miniaturization. The key to address these challenges is to advance our communication technology to match the multi-scale, multi-modal, and dynamic features of the natural IoE. To this end, we introduce a new communication device concept, namely the universal IoE transceiver, that encompasses transceiver architectures that are characterized by multi-modality in communication (with modalities such as molecular, RF/THz, optical and acoustic) and in energy harvesting (with modalities such as mechanical, solar, biochemical), modularity, tunability, and scalability. Focusing on these fundamental traits, we provide an overview of the opportunities that can be opened up by micro/nanoscale universal transceiver architectures towards realizing the IoE applications. We also discuss the most pressing challenges in implementing such transceivers and briefly review the open research directions. Our discussion is particularly focused on the opportunities and challenges pertaining to the IoE physical layer, which can enable the efficient and effective design of higher-level techniques. We believe that such universal transceivers can pave the way for seamless connection and communication with the universe at a deeper level and pioneer the construction of the forthcoming IoE landscape.Index Terms– Internet of Everything, Universal IoE Transceiver, Interoperability, Multi-modality, Hybrid Energy Harvesting, Molecular Communications, THz Communications, Graphene and related nanomaterials.

DeepNOMA: A Unified Framework for NOMA Using Deep Multi-Task Learning

Non-orthogonal multiple access (NOMA) will provide massive connectivity for future Internet of Things. However, the intrinsic non-orthogonality in NOMA makes it non-trivial to approach the performance limit with only conventional communication-theoretic tools. In this paper, we resort to deep multi-task learning for end-to-end optimization of NOMA, by regarding the overlapped transmissions as multiple distinctive but correlated learning tasks. First of all, we establish a unified multi-task deep neural network (DNN) framework for NOMA, namely DeepNOMA, which consists of a channel module, a multiple access signature mapping module, namely DeepMAS, and a multi-user detection module, namely DeepMUD. DeepMAS and DeepMUD are automatically trained in a data-driven fashion, and a multi-task balancing technique is then proposed to guarantee fairness among tasks as well as to avoid local optima. To further exploit the benefits of communication-domain expertise, we introduce constellation shape prior and inter-task interference cancellation structure into DeepMAS and DeepMUD, respectively. These sophisticated designs help to reduce the implementation complexity without sacrificing DNN’s universal function approximation property, which makes DeepNOMA a universal transceiver optimization approach. Detailed experiments and link-level simulations show that higher transmission accuracy and lower computational complexity can be simultaneously achieved by DeepNOMA under various channel models, compared with state-of-the-art.

USB Transceiver With a Serial Interface Engine and FIFO Queue for Efficient FPGA-to-FPGA Communication

This paper presents a universal serial bus (USB) transceiver with a serial interface engine (SIE) and an asynchronous first-in first-out (FIFO) queue for packet transformation and data transmission in field-programmable gate array (FPGA)-to-FPGA communication. The SIE block receives the data to be transmitted from the central processing unit of a PC and transfers those data to the universal transceiver macrocell interface, which handles data serialization and deserialization, bit stuffing, clock recovery, and clock synchronization. An asynchronous FIFO queue of 2 kilobits is designed to guarantee correct communication between two FPGA development boards. A parallel-in serial-out block converts parallel input data into serial data. A product identification (PID) check block determines whether the serial data are in the USB packet format. The cyclic redundancy check (CRC) checksums, namely CRC5 and CRC16, are presented with data check statements. After passing through the NRZI decoder, bit-unstuffing, PID check, and CRC16 blocks, the received serial data are converted into parallel output data by using a serial-in parallel-out block. The FPGA-to-FPGA communication design operates correctly. An application-specific integrated circuit (ASIC) of the USB transceiver is implemented using TSMC 0.18-μm CMOS technology. The gate counts, power consumption, operating frequency, and chip area of the ASIC are 14,547, 2.6742 mW, 50 MHz, and 0.7 × 0.67 mm 2 , respectively, at a supply voltage of 1.8 V and total pin number of 38.

Active wireless ultrawideband networks based on chaotic radio pulses

Active wireless networks with ultrawideband chaotic pulses used as the data carrier for wireless transmission are discussed. A universal transceiver module for nodes of active networks is proposed, designed, and studied. Various types of nodes based on this module are examined. The structure of active ultrawideband wireless networks and their operation principles are investigated. Examples of experimental networks based on the universal module are given, and their parameters are presented.